Route planning algorithms, as a core technology of intelligent and connected vehicles (ICVs), significantly enhance road safety and traffic efficiency. Fusing traffic data and edge server information into route planning algorithms enables ICVs to avoid road accidents and enhances their access to low-latency computational resources. However, developing a route planning approach for ICVs faces two major challenges: (i) learning anomaly distributions from traffic data is complicated due to the scarcity of anomaly datasets, and (ii) the large-scale of routes complicates the evaluation of computational resources. In this article, we propose a route planning approach with traffic data and edge server (RP-TDES) to address these above challenges. Specifically, the anomaly detection module of the RP-TDES approach integrates a generator that mines spatiotemporal features and a discriminator based on similarity measures. Both components are optimized through adversarial training to address the scarcity of anomalous events. In addition, to address the challenge of evaluating the computational resources for a entire route, we propose an evaluation method that considers the vehicle's mobility characteristics. Finally, we validate the effectiveness of our approach on both real-world and synthetic road networks, and the experiment results show that our approach outperforms the baseline in route planning in terms of vehicle travel time and edge service capability. Meanwhile, experiment results demonstrate that our anomaly detection model also outperforms baseline methods for accident detection.

Abstract Pedestrian re‐identification (re‐ID) is an important research direction in computer vision, with extensive applications in pattern recognition and monitoring systems. Due to uneven data distribution, and the need to solve clustering standards and similarity evaluation problems, the performance of unsupervised methods is limited. To address these issues, an improved unsupervised re‐ID method, called Enhanced Feature Representation and Robust Clustering (EFRRC), which combines EFRRC is proposed. First, a relation network that considers the relations between each part of the pedestrian's body and other parts is introduced, thereby obtaining more discriminative feature representations. The network makes the feature at the single‐part level also contain partial information of other body parts, making it more discriminative. A global contrastive pooling (GCP) module is introduced to obtain the global features of the image. Second, a dispersion‐based clustering method, which can effectively evaluate the quality of clustering and discover potential patterns in the data is designed. This approach considers a wider context of sample‐level pairwise relationships for robust cluster affinity assessment. It effectively addresses challenges posed by imbalanced data distributions in complex situations. The above structures are connected through a clustering contrastive learning framework, which not only improves the discriminative power of features and the accuracy of clustering, but also solves the problem of inconsistent clustering updates. Experimental results on three public datasets demonstrate the superiority of our method over existing unsupervised re‐ID methods.

A high-linearity down mixer with outstanding robust temperature tolerance for V-band applications is proposed in this paper. The mixer’s temperature robustness has been greatly enhanced by employing a negative temperature-compensation circuit (NTC) and a positive temperature-compensation circuit (PTC) in the transconductance ( g m ) stage and intermediate frequency (IF) output buffer, respectively. Benefiting from the active balun with enhanced g m and emitter negative feedback technique, the linearity of the mixer has been significantly improved. For verification, a double-balanced V-band mixer is designed and implemented in a 130 nm SiGe BiCMOS process. Measured over the local oscillator (LO) bandwidth from 57 GHz to 63 GHz, the mixer demonstrates a peak conversion gain (CG) of −0.5 dB, a minimal noise figure (NF) of 11.5 dB, and an input 1 dB compression point (IP 1 dB ) of 4.8 dBm under an LO power of −3 dBm. Furthermore, the measurements of CG, NF, and IP 1 dB exhibit commendable consistency within the temperature range of −55 °C to 85 °C, with fluctuations of less than 0.8 dB, 1 dB, and 1.2 dBm, respectively. From 57 GHz to 63 GHz, the measured LO-to-radio frequency (RF) isolation is better than 46 dB, the measured return loss at the RF port is > 29 dB, and at the LO port it exceeds 12 dB. With a 2.5 V supply voltage, the mixer power consumption is 15.75 mW, 18.5 mW, and 21 mW at temperatures of −55 °C, 25 °C, and 85 °C, respectively. Moreover, the mixer chip occupies a total silicon area of 0.56 mm 2 including all testing pads.

Compared with conventional analog circuit topology synthesis methods, the deep-reinforcement-learning (DRL)-based method features much higher synthesis efficiency while possessing the merit of strong generalization capability. However, this method cannot synthesize operational amplifiers that involve signal division. To address this critical limitation, this article presents new synthesis rules to guide the DRL-based synthesis process. In addition, to meet various design specifications requested by users, we further develop a smart circuit synthesis system, which can robustly return a solution (i.e., a feasible circuit topology with detailed device sizes) right away as long as the input design specifications are reasonable. A transfer learning (TL) scheme is proposed to reduce the computation overhead of training this system. The experimental results show the efficacy of our smart circuit synthesis system and TL scheme, confirming an advancement over the state-of-the-art approaches.