In this work, we present a thin-profile, efficient power delivery approach, including a voltage regulator with in-package power inductor and backside power delivery network (PDN). To meet 1-$\mathrm {W}/{\mathrm {mm}}^{2}$power-density target for high-performance computing (HPC) systems, a 25-high-$Q$-factor (300 MHz), 150-$\mu \text{m}$-thick, in-molding power inductor is provided for high-efficiency point-of-load (PoL) voltage regulation. Meanwhile, a novel analytical model for backside power delivery is developed for computer-aided-design (CAD) procedure to optimize the system efficiency. For the power flowing from bumps (57-$\mu \text{m} V_{\mathrm {DD}}$-bump pitch) and backside PDN to active devices, the area resistances contributed by backside PDN and the buried power rail (BPR) are 23% and 77%, respectively, if a 10-$\mu \text{m}$-horizontal-pitch nano- through-silicon via ($n$TSV) is available. The resulting impact on power dissipation is within 1% so negligible. A higher ratio (0.5) buck converter with maintained efficiency is combined to better benefit the external interconnect. The overall power delivery efficiency$\eta \,\,=83$% can be obtained for 1-$\mathrm {W}/{\mathrm {mm}}^{2}$power-density target. The power losses contributed by an air-core inductor, power switches, and PDN/BPR/redistribution layer (RDL) are 26%, 66%, and 8%, respectively.

We present a$\mu \text{m}$-thin-profile power delivery solution including a charge pump with integrated passives. Targeting 1 W/mm2or higher power density, a 2.5-D high-density metal-insulator-metal (MIM) capacitor deposited on high aspect ratio (HAR) (up to 5) oxide studs is proposed. With approximately 25-nm-thick HfAlOx dielectric, its measured capacitance density is 25.4 nF/mm2for a capacitor size ranging from 1/16 mm2to 1 mm2. This shows$3.6\times $density improvement compared with the planar MIM. Theoretically, 86 nF/[email protected] bias can be obtained if a 10-nm dielectric is deposited. Moreover, the measured leakage current density is within 65 pA/mm2at 1-V bias (negligible for a 1 W/mm2-power delivery). For a backside (BS) power delivery, this 2.5-D MIM capacitor can be realized by only three BS metal layers. This enables the low-cost and thin-profile delivery system ($\sim \!\!\mu \text{m}$thickness), and the whole power delivery efficiency including a 1/2-ratio charge pump is$\eta \,\,=84$%@1 W/mm2(>5% boost in the power efficiency).

In this work, a feasible charge pump structure with complete voltage conversion ratios (VCRs) of 1-2nis proposed. For a charge pump with off-chip capacitors for current-drive-capacity enhancement, some capacitors can be removed directly and the one in the following stage is utilized for charge storage. The proposed scheme only requires n flying capacitors and can achieve maximum integration. Based on 0.25 μm 5 V/12 V/24 V process, a three-stage topology has been verified by simulation as an example. It has been operated with VCRs of 1×-8× with only three flying capacitors. It has supplied at least 90 μA current with a maximum current of 3.33 mA. Meanwhile, a peak power efficiency of 84% has been achieved.

A switched-capacitor dc-dc voltage regulator that converts an input of 2.4-3.6 V to an output of 30 V has been designed to power display driver integrated circuits. A novel Fibonacci structure, named connect-point-shift, is proposed to improve the current drivability, which increases the minimum current drivability from 0.16 to 0.274 mA. This scheme saves the chip size by approximately 40% while providing equal current drivability as the traditional one. The power efficiency has been improved by 1%-7%, and a peak efficiency of 83.4% has been achieved. The adaptive-conversion-ratio has been adopted for ripple and efficiency improvement. A pulse skip regulator and a linear regulator are utilized to keep the output terminal of the charge pump stable at around 30 V. Their ripple, efficiency, load regulation, and line regulation are compared for further optimization. Theories of Degenerate State and state-space averaging are applied to validate the performance enhancement. This scheme has been fabricated and validated by a 0.11-μm 1.5 V/6 V/30 V process.