This paper proposes a novel and efficient model for the estimation of post-FEC BER for high-speed serial links using FEC codes such as RS (544, 514) in the presence of DFE error propagation. The model employs the Markov model for DFE error propagation and incorporates concepts from the Gilbert-Elliott model. Using various optimization techniques, including Markov state aggregation, burst tables, and adaptive neglect of rare cases, it achieves a computation time that is only 1.658% of that required by previous work for the post-FEC BER computation with RS (544, 514) FEC code and a 2-tap DFE. Furthermore, analyses demonstrate that its computation time increases less rapidly with respect to the number of DFE taps compared to previous works, indicating its better applicability for systems with more DFE taps or larger state spaces. Data measured from an FPGA-based behavior simulator proved that the model can accurately estimate post-FEC BER.

With the increasing speed and more stringent Bit Error Rate (BER) requirements of serial wireline links, FPGA-based SerDes (serializer/deserializer) simulation systems have gained widespread usage. As a fundamental component for BER simulation, there is a growing demand for Gaussian random number (GRN) generators that offer enhanced statistical accuracy, improved efficiency, and greater scalability. In this paper, we introduce a novel design methodology for GRN generators tailored for SerDes simulation systems. Unlike conventional approaches, this methodology treats GRNs as discrete values, is optimizable for specific GRN variances, supports pre-determined output ranges, and offers complete reconfigurability with respect to variance. A theoretical output range of$\pm 14\sigma$is exemplified. Synthesis results and statistical tests demonstrated that generators designed using the proposed method are statistically accurate while consuming low resources and providing complete reconfigurability.

In the process of microseismic monitoring, the accuracy of seismic phase picking has a great influence on the precision of seismic localization. Recently, neural network models have achieved satisfying results in seismic phase picking. But these models are mainly applicable to natural earthquakes. In this letter, we present a fully convolutional network for microseismic phase picking called MSNet. The performance of the model is improved from three aspects: model structure, training data, and training strategy. MSNet has two decoders to allow for auxiliary learning, and its structure is improved with reference to state-of-the-art fully convolutional network. Our training data derives from the Stanford Earthquake Dataset (STEAD). It is selected and processed to meet our requirements. In the training process, a special early stopping strategy is used to obtain the model with best generalization performance. The model is tested on fracture-induced microseismic monitoring data from a coal mine in Shaanxi Province, China. Methods for comparison include short- and long-time average ratio, the original PhaseNet and a retrained PhaseNet. The number of correct P picks of MSNet is 18.7% more than PhaseNet, and MSNet achieves a 16.2% higher precision than PhaseNet on S phase. The event locating results verified the accuracy of MSNet. Our method provides an idea to build a microseismic phase picking model with better generalization performance and lower labor cost.

In this article, a configurable and highly flexible four-level pulse amplitude modulation (PAM4) serializer/deserializer (SerDes) simulation system based on a field-programmable gate array (FPGA) is designed, which can simulate all bit rates currently supported by actual chips, such as 112 Gb/s. Compared to software simulation systems, the efficiency of this hardware simulation system is greatly improved. This simulation system allows parameterized configuration, and when paired with a CPU, it can save simulation data from various stages. Therefore, this simulation system can help integrated circuit (IC) designers save time and resources, design SerDes chips under different channel conditions, explore the error model of SerDes chips, and design improved equalization and forward error correction (FEC) schemes. Because some existing SerDes module algorithms are not publicly accessible, the commonly used SerDes module algorithms are summarized in this article, and some of them are modified. First, a parallel architecture for a scrambler/descrambler is designed using the Chisel language, which can be used to construct synchronous or asynchronous scramblers/descramblers of any parallel stage. Second, for the designed simulation system, the sign-to-sign Mueller–Muller phase detector (MMPD) from nonreturn-to-zero (NRZ) to PAM4 is introduced, eliminating the detection of rising or falling edges and instead performing phase detection between any two unit intervals (UIs). Experiments on the designed simulation system show a maximum signal-to-noise ratio (SNR) error of 0.05151 dB compared to theoretical results under the same bit error rate (BER) condition and a mean error of 0.03488 dB. The simulation results agree with the theoretical prediction.

Abstract Time jitter analysis is an important means to evaluate the performance of a high‐speed serial communication system. Clock data recovery (CDR) is a critical component of a high‐speed serial link that recovers the reference clock from a signal for jitter analysis. Traditional studies focused on CDR technology for the non‐return‐to‐zero pattern based on a hardware design, but little work has been devoted to the software CDR especially for the four‐level pulse amplitude modulated (PAM4) encoded data signals. This study proposes a new software algorithm to recover clocks from PAM4 signals that is capable of extracting synchronous clocks from PAM4 signals to design an ideal software phase‐locked loop for clock recovery. The proposed algorithm extracts more types of data transition edges than hardware methods to avoid the loss of jitter information. Besides, the algorithm designs an ideal phase‐locked loop to improve the filtering accuracy. This algorithm has been implemented in MATLAB, and shows superior performance to that of conventional CDR technology.

This manuscript introduces a genetic algorithms (GA) method to design a kind of portable low natural frequency geophone which widely used in surveying deep geological structure. We attach a new electromagnetic feedback network to the two output poles of moving-coil geophone to improve the performance of low-frequency response. Because the feedback network is a complicated active analog circuit, it's very difficult to design an optimized one by classical circuit theory. So, GA is novelly used to get an optimized frame and parameters of the network. We use PSPICE to get the netlist files of the network and to evaluate the individual fitness. Simulation and test results have shown that we can satisfactorily move the natural frequency of geophone from 10Hz to 5Hz through the feedback network gotten by GA.