Low-complexity detection schemes are studied for additive white Gaussian noise channels with an unknown and unbounded offset constant over each memory read. Detectors based on the Pearson distance are analyzed, and a new lower bound on the word error rate of Modified Pearson (MP) detection is derived. Three novel detectors are proposed: the Simplified Pearson (SP), the Ultra-Simplified Pearson (USP), and the Adjusted-Threshold (AT) detectors. The USP and AT detectors are designed to be robust against destructive readings. The proposed schemes are particularly suited for memory systems employing ramp-reading architectures. The analysis demonstrates that the proposed detectors achieve competitive error-rate performance with significantly reduced complexity compared to MP detection.

This work investigates the error performance of detection schemes based on the minimum Pearson distance in the context of additive white Gaussian noise channels with unknown and unbounded offset, constant throughout each channel use. We derive a lower bound on the word error rate under modified Pearson (MP) detection. Additionally, we introduce a new and low-complexity detection strategy, namely the Simplified Pearson (SP) detector. We analyze and compare the error performance of the SP detector with that of the MP detector.

We propose the Active Compute Memory (ACM), a near-memory-processing architecture capable of performing key–value sort directly in the DRAM. In the ACM architecture, sort is merely the writing of data into memory with one addressing protocol (perspective) and reading it back with different perspective. The first perspective is conventional, based on the data address; the second perspective is the sorted order. The ACM requires additional tables to store the meta-data and moderate control logic enhancements that can be implemented directly in the DRAM silicon. By these modest enhancements to DRAM, ACM exploits the parallelism inherently available in the row buffer to enable sort with$O(n)$complexity. This leads to an order of magnitude improvement in ACM performance and energy compared to conventional$O(n\log{}n)$CPU-centric sort algorithms. The ACM also shows superior performance compared to other near-memory sort accelerators. This is because the ACM processing is done near the row buffer and it exploits much lower memory access latency, higher bandwidth and wider parallel processing. The sort operation covered in this paper is just an example of an address management operation that can be efficiently implemented directly in the DRAM silicon. We release as an open source the simulation infrastructure for the ACM performance and energy modeling. We would encourage the community to use it, adapt it to other PIM proposals, and share their own evaluations.

Emerging memory technologies (like PCM, MRAM and 3D XPoint) can make data storage as fast as the rest of the system. But to cope with the reliability targets of storage applications, error correcting codes (ECCs) able to correct many errors might be needed anyway. Hierarchical codes, ECCs enabling two levels of correction, can be good candidates to satisfy these reliability targets, without impacting (on average) the low-latency characteristics of these technologies. In particular, an Ultra-Fast (UF) ECC can be used as first trial as long as it is able to flag its failures with high probability and low latency. In this paper we design an UF-ECC able to produce a check for incorrect decoding with probability lower than the typical target uncorrectable bit-error rate (UBER) of storage applications (e.g. 1e-15) and with a latency comparable with the UF-ECC correction process.

High-performance storage class memories could benefit from a fast decoding error correcting code (ECC), able to correct a few errors in just a few nanoseconds. The class of BCH codes provides excellent candidates to play this role. The low latency requirement prevents adopting iterative or sequential processes in the encoding and decoding phases-as traditionally done for storage application based on Flash NAND technology. Therefore, we propose an architecture for fast decoding of double and triple ECCs. In our architecture, any time-consuming iterative computation is eliminated, and the most complex evaluations are isolated and carried in parallel with the other terms, to avoid bottlenecks in the decoder. In particular, the error locator polynomial is computed by a combinatorial logic, and its roots are searched by testing all the bits simultaneously. Here, we describe a gate-level design of these architectures. We also give an in-depth analysis of hardware-oriented implementations of finite field operations, and of bases for element representation.