Many Artificial Intelligence algorithms (e.g. Convolutional Neural Networks - CNNs) can be modeled as a collection of functions which communicate with each other according to a directed acyclic graph. The main goal of this paper is to optimize the execution of CNNs on real-time embedded systems based on a multicore architecture with scratchpad memory. In a typical multicore platform, cores share a complex memory hierarchy with one or more levels of cache memories, leading to potential interference and contention on the shared communication buses. In these architectures, it is very difficult to bound the tasks' execution time and the communication delay, due to the unpredictable behavior of the cache subsystem. To reduce contention, it is possible to use architectures based on scratchpads, where every processor has a dedicated programmable fast memory to perform its local computations, and data is moved between the main memory and the local memories according to a timed schedule. In this paper, we study the problem of allocating CNN inference functions to processor cores, and scheduling the execution and memory communications. We propose an Integer Linear Programming (ILP) model that accounts for both the cost of copying data to and from scratchpad memories and the parallel computation costs on the cores, with the goal of meeting real-time temporal constraints. We propose an abstract model and two different optimization techniques, offering a trade-off between analysis time and performance. To evaluate our approach, we compare its effectiveness to classic techniques for accelerating matrix multiplication, using benchmarks from the literature. Our results demonstrate that our ILP constraints provide significant improvements in optimizing realistic CNNs.

Commercial-off-the-shelf (COTS) platforms feature several cores that share and contend for memory resources. In real-time system applications, it is of paramount importance to correctly estimate tight upper bounds to the delays due to memory contention. However, without proper support from the hardware (e.g. a real-time bus scheduler), it is difficult to estimate such upper bounds.This work aims at avoiding contention for a set of tasks modeled using the Predictable Execution Model (PREM), i.e. each task execution is divided into a memory phase and a computation phase, on a hardware multicore architecture where each core has its private scratchpad memory and all cores share the main memory. We consider non-preemptive scheduling for memory phases, whereas computation phases are scheduled using partitioned preemptive EDF. In this work, we propose three novel approaches to avoid contention in memory phases: (i) a task-level time-triggered approach, (ii) job-level time-triggered approach, and (iii) on-line scheduling approach. We compare the proposed approaches against the state of the art using a set of synthetic experiments in terms of schedulability and analysis time. Furthermore, we implemented the different approaches on an Infineon AURIX TC397 multicore microcontroller and validated the proposed approaches using a set of tasks extracted from well-known benchmarks from the literature.

Real-time and latency sensitive applications such as autonomous driving, feature an increasing need of computational power that traditional multi-core platforms can not provide. For this purpose, many heterogeneous embedded platforms have been released recently. They offer a set of diverse processing elements (e.g. GPUs, DSPs, ASICs, etc...) in order to manage the computational demands of data hungry applications. The system engineer, therefore, can choose the fittest processing element for each specific subtask. In this context, timing constraints and related task models are of paramount importance.The HPC-DAG (Heterogeneous Parallel Directed Acyclic Graph) task model has been recently proposed to capture real-time workload execution on modern heterogeneous platforms. It expresses the Instruction Set Architecture (ISA) heterogeneity across the different compute accelerators, but also their differences in terms of possible scheduling policies such as preemption.In this paper, we propose a time-table scheduling approach to allocate and schedule a set of HPC-DAG tasks onto a set of heterogeneous cores, by the mean of Integer Linear Programming (ILP). Our design allows the system engineer to handle heterogeneity of resources, of on-line execution costs, and of a part of the tasks and sub-tasks allocation to cores. It improves the solving time compared to the state of the art by gradually exploring the design space.

Recent commercial hardware platforms for embedded real-time systems feature heterogeneous processing units and computing accelerators on the same System-on-Chip. When designing complex real-time applications for such architectures, the designer is exposed to a number of difficult choices, like deciding on which compute engine to execute a certain task, or what degree of parallelism to adopt for a given function. To help the designer exploring the wide space of design choices and tune the scheduling parameters, we propose a novel real-time application model, called HPC-DAG (Heterogeneous Parallel Condition Directed Acyclic Graph Model), specifically conceived for heterogeneous platforms. An HPC-DAG allows the system designer to specify alternative implementations of a software component for different processing engines, as well as conditional branches to modelif-then-elsestatements. We also propose a schedulability analysis for the HPC-DAG model and a set of heuristic allocation algorithms aimed at improving schedulability for latency sensitive applications. Our analysis takes into account the cost of preempting a task, which can be non-negligible on certain processors. We show the use of our approach on a realistic case study, and we demonstrate its effectiveness by comparing it with state-of-the-art algorithms previously proposed in literature.

Heterogeneous hardware platforms are often used for implementing complex critical real-time applications, like Advanced driver-assistance systems (ADAS) and autonomous driving. Typically, they are composed of CPU hosts and a set of accelerators. To better support real-time workloads, several hardware accelerators have evolved to allow preemption for computationally intensive tasks, such as GPUs. However, their preemption costs can be very high compared to classical CPU preemption, and therefore must be taken into account at design time and in the scheduling analysis. In this paper, we address mainly two tightly correlated problems: (i) task allocation for a set of real-time tasks, modeled by conditional directed acyclic graphs (C-DAG), onto multiprocessor platforms under partitioned preemptive Earliest Deadline First scheduling, assuming a non-negligible cost of preemption, and (ii) intermediate deadlines and offsets assignments to real-time C-DAGs, so to remove unnecessary preemption and reduce the total preemption overhead. The effectiveness of the proposed technique is evaluated using a large set of synthetic tasks sets.

Many task models have been proposed to express and analyze the behavior of real-time applications at different levels of precision. Most of them target sequential applications with no support for parallelism. The digraph task model is one of the most general ones, as it allows modeling arbitrary directed graphs (digraphs) for sequential job releases. In this paper, we extend the digraph task model to support intra-task parallelism. For the proposed parallel multi-mode digraph model, we derive sufficient schedulability tests and a dichotomic search to improve the test pessimism for a set of n tasks onto a heterogeneous single-ISA multi-core platform. To reduce the computational complexity of the schedulability test, we also propose heuristics for (i) partitioning parallel digraph tasks onto the heterogeneous cores, and (ii) assigning core operating frequencies to reduce the overall energy consumption, while meeting real-time constraints. The effectiveness of the proposed approach is validated with an exhaustive set of simulations.