Panoramic roaming with HMDs provides an immersive VR experience and the realism of user’s navigation in panoramic virtual environments (VEs) can be further enhanced by real-walking locomotion technology. However, the mismatched viewpoint height & fluctuation with the user’s visual senses may lead to perceptual conflicts during real-walking interaction. We conducted a series of user studies to investigate how viewpoint height & fluctuation affect the walking perception of users by real-walking interaction to navigate panoramic VEs and constructed a virtual camera motion model of viewpoint fluctuation and eyetracking compensation for walking behavior in panoramic virtual roaming. It was found that mismatched viewpoint fluctuation triggered generalized discomfort in participants and that participants preferred virtual viewpoint heights below eye level when roaming in panoramic VEs by real-walking. Considering these findings, we proposed viewpoint adaptive adjustment method based on visual manipulation and conducted a preliminary evaluation, which showed that the proposed method can effectively mitigate the conflict between the visual system and other sensory systems. It made that panoramic VEs constructed at a certain fixed height are rendered universal for users with different eyelevel heights and viewpoint fluctuation is matched to the undulation of their center of gravity during real-walking interaction.

Online fitness training, with its affordability and flexibility, offers a convenient way for individuals to engage in regular workouts that promote physical and mental health. Yet, learning fitness motions in this way presents various challenges and may not always be as effective as in-person training. To address the practical demands of motion learning, we conducted a systematic survey and accordingly proposed a four-stage self-learning genre that integrates immersive virtual reality (VR) environments with motion skill learning theories, strategies, and expert experience. Herein, we merged progressive structures and multi-level visual cues to enhance instruction, and proposed a fine-grained motion analysis method to provide adaptive correction feedback during training. Utilizing a Taichi training platform with the genre embedded, we systematically validated the effectiveness of the genre, and examined the potential impact of VR content presentation form on motion learning among different age groups, as well as their preferences and focus on VR fitness training genre design. Results from the quantitative analysis, qualitative evaluation, and case study showed that the 360° video-based VR content brought more positive motion learning performance and user experiences than the fully-simulated VR used in many previous studies. The proposed genre demonstrated outstandingly performance, experience, and usability, with each stage and design playing an effective role. Moreover, we offer several design considerations for VR fitness systems targeting diverse age groups, providing beneficial insights for VR development in the sports and health-related fields.

Routing is a crucial stage in a modern design automation tool flow for advanced technology nodes. Works in the recent open literature tend to divide routing into separate global routing (GR) and detailed routing (DR) steps without addressing the correlation issues (e.g., local nets) between these two steps. In this work, we present TritonRoute-WXL (TR-WXL), a unified global-detailed router capable of delivering design rule check-clean routing solutions in commercial sub-16-nm technologies. The major contributions of TR-WXL include an end-to-end routing framework that closely connects GR and DR, and an improved DR flow. With a code release under a permissive open-source license, TR-WXL achieves unparalleled solution quality in terms of DR and global-detailed routing (GDR) as compared to known best solutions from all published academic routers.

Detailed routing is a dead-or-alive critical element in design automation tooling for advanced node enablement. However, very few works address detailed routing in the recent open literature, particularly in the context of modern industrial designs and a complete, end-to-end flow. The ISPD-2018 Initial Detailed Routing Contest addressed this gap for modern industrial designs, using a realistic design rules set. In this work, we present TritonRoute, a detailed router capable of delivering a DRC-clean routing solution. The key contributions of TritonRoute include an in-memory router database, along with an end-to-end detailed routing scheme that is capable of comprehending connectivity and design rule constraints, with every key detail revealed by a code release under a permissive open-source license. We evaluate our router using the official ISPD-2018 benchmark suite and show that TritonRoute achieves an unprecedented solution quality-improved wirelength and via count, and an extremely low level of design rule violations (DRCs). Compared to the known best detailed routing solutions from all published academic detailed routers, TritonRoute improves wirelength by up to 0.8% (avg. 0.4%), via count by up to 16.1% (avg. 9.3%), and DRCs by up to 100% (avg. 92.0%).

Pin accessibility has been widely studied, particularly in recent works that span detailed placement optimization, standard cell layout optimization and new design rule-aware access model. However, to our knowledge, no previous work has described a full solution for pin access analysis, with validations on real detailed routing benchmarks. This paper presents a complete, robust, scalable and design rule-aware dynamic programming-based pin access analysis framework that is capable of both standard cell-based and instance-based pin access analysis. Integration into the open-source TritonRoute router results in superior solution quality compared to previous best-known results for the official ISPD-2018 benchmark suite.

Summary The evaluation of Internet advertising effectiveness plays an important role in network marketing at this stage. The evaluation criteria of Internet advertising effectiveness mostly use proceeds as an indicator, ignoring the brand effect generated by Internet advertising, making it difficult for researchers to further study the effect of Internet advertising. With the updating and iteration of technical theory, it is an urgent task to find a new criteria to measure Internet advertising effectiveness. At present, the research on Internet advertising effectiveness research is based on the analysis of nondifferentiation category. The research on user click behavior is a holistic analysis of the whole web page. This global coverage research is difficult to present the behavior characteristics of users in the web page. In response to the above problems, the impression space is proposed to measure Internet advertising effectiveness. Firstly, the fuzzy classification theory is used to digitize the user category data, the user type is divided by probability distribution, and the distribution of web page interest regions is divided by gaze time and page layout to further study the click‐and‐effect relationship of different users and the user browsing time series.Then, establish multimodal multifactors to build an impression space model to measure Internet advertising effectiveness. The experimental results show that the accuracy of the constructed impression space model for the evaluation of Internet advertising effectiveness reaches 92.4%, and the impression space is more effective as the evaluation of Internet advertising effectiveness.

Web ad effect evaluation is a challenging problem in web marketing research. Although the analysis of web ad effectiveness has achieved excellent results, there are still some deficiencies. First, there is a lack of an in‐depth study of the relevance between advertisements and web content. Second, there is not a thorough analysis of the impacts of users and advertising features on user browsing behaviors. And last, the evaluation index of the web advertisement effect is not adequate. Given the above problems, we conducted our work by studying the observer's behavioral pattern based on multimodal features. First, we analyze the correlation between ads and links with different searching results and further assess the influence of relevance on the observer's attention to web ads using eye‐movement features. Then we investigate the user's behavioral sequence and propose the directional frequent‐browsing pattern algorithm for mining the user's most commonly used browsing patterns. Finally, we offer the novel use of “memory” as a new measure of advertising effectiveness and further build an advertising memory model with integrated multimodal features for predicting the efficacy of web ads. A large number of experiments have proved the superiority of our method.

In advanced technology nodes, IC implementation faces increasing design complexity as well as ever-more demanding design schedule requirements. This raises the need for new decomposition approaches that can help reduce problem complexity, in conjunction with new predictive methodologies that can help avoid bottlenecks and loops in the physical implementation flow. Notably, with modern design methodologies it would be very valuable to better predict final placement of the gate-level netlist: this would enable more accurate early assessment of performance, congestion and floorplan viability in the SOC floorplanning/RTL planning stages of design. In this work, we study a new criterion for the classic challenge of VLSI netlist clustering: how well netlist clusters "stay together" through final implementation. We propose use of several evaluators of this criterion. We also explore the use of modularity-driven clustering to identify natural clusters in a given graph without the tuning of parameters and size balance constraints typically required by VLSI CAD partitioning methods. We find that the netlist hypergraph-to-graph mapping can significantly affect quality of results, and we experimentally identify an effective recipe for weighting that also comprehends topological proximity to I/Os. Further, we empirically demonstrate that modularity-based clustering achieves better correlation to actual netlist placements than traditional VLSI CAD methods (our method is also 4X faster than use of hMetis for our largest testcases). Finally, we show a potential flow with fast "blob placement" of clusters to evaluate netlist and floorplan viability in early design stages; this flow can predict gate-level placement of 370K cells in 200 seconds on a single core.

A diffusion break (DB) isolates two neighboring devices in a standard cell-based design and has a stress effect on delay and leakage power. In foundry sub-10nm design enablements, device performance is changed according to the type of DB - single diffusion break (SDB) or double diffusion break (DDB) - that is used in the library cell layout. Crucially, local layout effect (LLE) can substantially affect device performance and leakage. Our present work focuses on the 2nd DB effect, a type of LLE in which distance to the second-closest DB (i.e., a distance that depends on the placement of a given cell's neighboring cell) also impacts performance of a given device. In this work, we implement a 2nd DB-aware timing and leakage analysis flow, and show how a lack of 2nd DB awareness can misguide current optimization in place-and-route stages. We then develop 2nd DB-aware leakage optimization and detailed placement heuristics. Experimental results in a scaled foundry 14nm technology indicate that our 2nd DB-aware analysis and optimization flow achieves, on average, 80% recovery of the leakage increment that is induced by the 2nd DB effect, without changing design performance.

We describe the planned Alpha release of OpenROAD, an open-source end-to-end silicon compiler. OpenROAD will help realize the goal of "democratization of hardware design", by reducing cost, expertise, schedule and risk barriers that confront system designers today. The development of open-source, self-driving design tools is in and of itself a "moon shot" with numerous technical and cultural challenges. The open-source flow incorporates a compatible open-source set of tools that span logic synthesis, floorplanning, placement, clock tree synthesis, global routing and detailed routing. The flow also incorporates analysis and support tools for static timing analysis, parasitic extraction, power integrity analysis, and cloud deployment. We also note several observed challenges, or "lessons learned", with respect to development of open-source EDA tools and flows.

Power Delivery Network (PDN) is one of the most challenging topics in modern VLSI design. Due to aggressive technology node scaling, resistance of back-end-of-line (BEOL) layers increases dramatically in sub-10nm VLSI, causing high supply voltage (IR) drop. To solve this problem, pre-placed or post-placed power staples are inserted in pin-access layers to connect adjacent power rails and reduce PDN resistance, at the cost of reduced routing flexibility, or reduced power staple insertion opportunity. In this work, we propose dynamic programming-based single-row and double-row detailed placement optimizations to maximize the power staple insertion in a post-placement flow. We further propose metaheuristics to improve the quality of result. Compared to the traditional post-placement flow, we achieve up to 13.2% (10mV ) reduction in IR drop, with almost no WNS degradation.

In advanced nodes, routing has become more and more complicated. The ISPD-2018 and ISPD-2019 Initial Detailed Routing Contests [10] [11] were held to bridge the detailed routing gap between academia and industry by releasing benchmarks using industry tool and libraries. The industry-standard LEF/DEF-based benchmark suite has inspired a new generation of large-scale academic implementations of detailed routing frameworks considering complex design rules. At the same time, efforts such as the OpenROAD [1] and the IEEE CEDA DATC Robust Design Flow (RDF) [3] [8] projects aim to provide full RTL-to-GDS flows as the basis for academic research and improved academic-industry interfaces; the former project is moreover developed as open source. In these efforts, routing is clearly one of the most important stages. The ICCAD-2019 LEF/DEF-based open-source global routing contest revisits the global routing topic treated in the ISPD-2007 and ISPD-2008 contests [12] [13], encouraging researchers to contribute open-source global routers that are industry-proven and well-correlated in advanced-node designs.

The Nesterov's method approach to analytic placement has recently demonstrated strong solution quality and scalability. We dissect the previous implementation strategy and show that solution quality can be significantly improved using two levers: 1) constraint-oriented local smoothing and 2) dynamic step size adaptation. We propose a new density function that comprehends local overflow of area resources; this enables a constraint-oriented local smoothing at per-bin granularity. Our improved dynamic step size adaptation automatically determines step size and effectively allocates optimization effort to significantly improve solution quality without undue runtime impact. Our resulting global placement tool, RePlAce, achieves an average of 2.00% half-perimeter wirelength (HPWL) reduction over all best known ISPD-2005 and ISPD-2006 benchmark results, and an average of 2.73% over all best known modern mixed-size (MMS) benchmark results, without any benchmark-specific code or tuning. We further extend our global placer to address routability, and achieve on average 8.50%-9.59% scaled HPWL reduction over previous leading academic placers for the DAC-2012 and ICCAD-2012 benchmark suites. To our knowledge, RePlAce is the first work to achieve superior solution quality across all the ISPD-2005, ISPD-2006, MMS, DAC-2012, and ICCAD-2012 benchmark suites with a single global placement engine.

Layout-dependent effect causes variation in device performance as well as mismatch in model-hardware correlation in sub-10 nm nodes. In order to effectively explore the power-performance envelope for IC design, cell libraries must provide cells with different diffusion heights, leading to neighbor diffusion effect (NDE) due to inter-cell diffusion height change (diffusion steps). Special filler cells can protect against steps to functional cells, but with nontrivial area overhead. In this paper, we develop dynamic programming (DP)-based single-row and multi-row (MR) detailed placement optimizations that optimally reduce inter-cell diffusion steps to mitigate the impacts of NDE. Compared to previous works, our algorithms are capable of exploring richer solution spaces as they support cell flipping, relocating, and reordering across cell rows; we also consider cell displacement, flipping, and wirelength costs. Notably, to our knowledge, our MR DP-based optimization algorithm is the first to optimally handle inter-row cell relocating and reordering. We also explore various metaheuristic configurations to further improve the solution quality. Last, we develop a timing-aware approach, which is capable of creating intentional steps that can potentially improve the drive strength of critical cells. The optimality is in terms of maximum diffusion step reduction, for given displacement range, reordering range and cell variants. Additionally, the above range definitions, including the definition of the ordering of cells, depend on assumptions described in Sections IV and V.

Detailed routing is a dead-or-alive critical element in design automation tooling for advanced node enablement. However, very few works address detailed routing in the recent open literature, particularly in the context of modern industrial designs and a complete, end-to-end flow. The ISPD-2018 Initial Detailed Routing Contest addressed this gap for modern industrial designs, using a reduced design rules set. In this work, we present TritonRoute, an initial detailed router for the ISPD-2018 contest. Given route guides from global routing, the initial detailed routing stage should generate a detailed routing solution honoring the route guides as much as possible, while minimizing wirelength, via count and various design rule violations. In our work, the key contribution is intra-layer parallel routing, where we partition each layer into parallel panels and route each panel using an Integer Linear Programming-based algorithm. We sequentially route layer by layer from the bottom to the top. We evaluate our router using the official ISPD-2018 benchmark suite and show that we reduce the contest metric by up to 74%, and on average 50%, compared to the first-place routing solution for each testcase.

The NP-hard Rectilinear Steiner Minimum Tree (RSMT) problem has been studied in the VLSI physical design literature for well over three decades. Fast estimators of RSMT cost (which reflects routed wirelength) are a required ingredient of modern physical planning and global placement methods. Constructive estimators build heuristic RSMTs whose costs are used as wirelength estimates; notably, these include FLUTE[8]. Analytic and lookup table-based estimators include the methods of Cheng[7] and Caldwell et al. [3]; the latter is based on both the number of points and the aspect ratio of the pointset in the RSMT instance. We observe that the physical design literature has numerous evaluations of RSMT heuristics and estimators on random pointsets, and that the relative merits of heuristics and estimators have been determined based on this use of random pointsets. In this paper, we show that a pointset attribute which we call L-ness highlights the difference between real placements and random placements of net pins. We explain why placements of netlists in practice result in pointsets with much higher L-ness than random pointsets, and we confirm this difference empirically for both academic and commercial placement tools. We further present an improved lookup table-based RSMT cost estimator that includes an L-ness parameter. Last, we illustrate how differences between Steiner tree heuristics can change depending on whether real or random pointsets are used in the evaluation.

Aggressive pitch scaling in sub-10nm nodes has introduced complex design rules which make routing extremely challenging. Cell architectures have also been changed to meet the design rules. For example, metal layers below M1 are used to gain additional routing resources. New cell architectures wherein inter-row M1 routing is allowed force consideration of vertical alignment of cells. In this work, we propose a mixed-integer linear programming (MILP)-based, detailed placement optimization to maximize direct vertical M1 routing utilization for congestion and wirelength reduction.

In sub-10nm, nodes, a change or step in diffusion height between adjacent standard cells causes yield loss as well as a form of model-hardware miscorrelation called neighbor diffusion effect (NDE). Cell libraries must inevitably have multiple diffusion heights (numbers of fins in PFETs and NFETs) in order to enable flexible exploration of the power-performance envelope for design. However, this brings step-induced risks of NDE, for which guardbanding is costly, as well as yield loss. Special filler cells can protect against harmful NDE effects, but are costly in terms of area. In this work, we develop dynamic programming-based single-row and double-row detailed placement optimizations that optimally minimize the impacts of NDE. Our algorithms support a richer set of cell movements than in previous works - i.e., flipping, relocating and reordering within the original row; we also consider cell displacement and flipping costs. Importantly, to our knowledge, our dynamic programming-based optimal detailed placement algorithm is the first to handle multiple rows with multiple-height cells that can be reordered. We further develop a timing-aware approach, which is capable of recovering (or, improving) the worst negative slack (WNS) by creating additional diffusion steps around timing-critical cells.

Self-aligned multiple patterning, due to its low overlay error, has emerged as the leading option for 1-D gridded back-end-of-line (BEOL) in sub-14-nm nodes. To form actual routing patterns from a uniform “sea of wires,” cut masks are needed for line-end cutting or realization of space between routing segments. The line-end cutting results in nonfunctional (i.e., dummy fill) patterns that change wire capacitance, and hence design timing and power. Therefore, to remove such dummy fill patterns, extra 2-D block masks are used. However, 2-D block masks cannot remove arbitrary dummy fill patterns, due to design rule constraints on the block mask shapes. In this paper, we address the timing-aware optimization of 2-D block mask layouts under various sets of mask rules that are derived from mask patterning technology options (e.g., 193i and 193d) for foundry 7-/5-nm (N7/N5) BEOL. Our central contribution is a mixed integer linear programming (MILP) optimization that minimizes timing impact due to dummy metal segments while satisfying block mask rules and metal density constraints. We also propose a distributed optimization flow to improve the scalability. With our optimizer, we recover up to 84% of the worst negative slack impact from dummy segments, with up to 64% dummy removal rate. We further extend our MILP to a co-optimization of cut and block masks. This paper gives new insights into fundamental limits of benefit from emerging cut and block mask technology options.

Clock network power reduction is critical in modern SoC designs. Application of flop trays (i.e., multi-bit flip-flops) can significantly reduce the number of sinks in a clock network, and thus reduce the number of clock buffers, clock wirelength, and clock network power. Shared inverters within flop trays also reduce power at the flip-flop level. However, large-size flop trays typically induce placement and routing congestion, and impose additional placement constraints on their fanin/fanout logic cones; this results in power overheads on datapaths. At the same time, to our knowledge, few previous works have studied flop trays with more than four bits. The “chicken-and-egg” loop between flop tray generation and placement optimization is another challenge to flop tray-based design [7]. In this work, we propose an optimization flow to generate and place flop trays from a library of arbitrary given sizes and aspect ratios (ARs), to achieve clock network power reduction. Our optimization starts with an initial placement solution using only single-bit flops. It then performs capacitated K-means clustering to generate solutions with different flop tray sizes and ARs. More specifically, we iteratively use (i) min-cost flow to cluster flops, and (ii) a linear programming-based optimization to determine locations of the generated flop trays. Last, we formulate an integer linear program to select the best combination of flop tray solutions (i.e., sizes and placements) with minimum displacement and number of isolated sinks. Our optimization is aware of flop tray sizes and ARs, as well as timing-critical start-end pairs. Results in foundry 28FDSOI technology show up to 32% total block power reduction as compared to designs using only single-bit flops, up to 16% total block power reduction over designs with flop trays generated by logical clustering during synthesis, and 13% clock power reduction on average compared to the previous work in [10].