This paper presents a symmetric correlated coding (SCC) scheme and the corresponding high-density transceiver that deliver 7-bit data over 8 lanes. The SCC method implements the 7-bit data encoding jointly in 8 correlated channels which improves the pin efficiency up to 87.5%. Besides, as an advanced chord signaling, the SCC exhibits the immunity to crosstalk, common-mode noise (CMN) and simultaneous switching noise (SSN). The proposed SCC transceiver innovates a SCC source-series-terminated (SST) driver that maintains an unchanged bandwidth even with a low-voltage power supply, and the CTLE decoder adopts the active inductor to compensate the channel loss. Prototyped in 28-nm CMOS, the proposed wireline transceiver using SCC method supports a maximum data rate of$7\times 10$Gb/s with a bit error rate (BER) <1e−12, achieving a data rate density (DRD) up to 61.4 Gb/s/mm. The SCC transceiver dissipates 99.4 mW with the energy efficiency of 1.42 pJ/bit.

This paper describes an adaptive duo-binary four-level pulse amplitude modulation (Duo-PAM4) detector that significantly reduces the bit error rate (BER) of the conventional wireline transceivers under high insertion loss (IL) channels. The parallel maximum likelihood sequence detection (MLSD) combined with parallel feed-forward equalization (FFE) is proposed to generate, equalize, and detect Duo-PAM4 signals, thus reducing BER compared to conventional decision feedback equalizer (DFE) and slicers. The proposed reduced branch MLSD reduces power consumption compared to MLSD. An improved delay zero-forcing algorithm for Duo-PAM4 is proposed to achieve fast convergence of the FFE tap coefficients, reducing convergence time by up to 72.5% compared to conventional ZF algorithms for Duo-PAM4. Both the proposed and conventional detectors are implemented in a 28-nm CMOS process at 56 Gb/s and 38-dB insertion loss. The FFE+MLSD and FFE+RB-MLSD reduce the BER by two orders of magnitude compared to conventional FFE+DFE+slicer. The RB-MLSD reduces power consumption by 21.1% compared to conventional MLSD. The detector can be easily migrated to 112Gb/s or 224Gb/s transceivers.

To solve the high bit error rate (BER) problem of conventional 56-Gb/s nonreturn-to-zero (NRZ) transceivers under high-insertion loss (IL) channels, this study proposes a high-speed adaptive duobinary (DB) digital detector based on the feed-forward equalizer (FFE) and the maximum likelihood sequence detector (MLSD). In this detector, adaptive FFE is combined with channel characteristics to generate DB signals and complete equalization, thus extending the transmission bandwidth and eye height and allowing a larger sampling phase offset. The parallel MLSD is used to complete the detection and decoding of DB signals to reduce the BER. An adaptive algorithm is proposed to avoid the long convergence time of the conventional zero-forcing (ZF) algorithm applied to the DB detector, so that it can be applied to various bit rates and IL channels. In this study, the verification of this DB detector is accomplished at 56 Gb/s. The platform based on a 56-Gb/s analog front-end chip (AFEC) and field-programmable gate array (FPGA) proves that the detector can work well in 12–56 Gb/s and multiple IL channels. The BER was less than 2e-8 at 56 Gb/s on −42-dB channel loss at 28 GHz. The structure can be well used for higher rate transceivers, such as 112 Gb/s.

To solve the problem of high bit error rate (BER) due to high inter-symbol interference (ISI) in high-speed wireline transceivers, this paper proposes a low-complexity adaptive reduced-state sequence detector (ARSSD). The detector is based on the maximum likelihood sequence detection (MLSD) to reduce the detection bit error rate (BER), adopts the ISI parameter acquisition method based on the zero-forcing algorithm to achieve the adaptive detector parameters, and combines the viterbi algorithm and the set partitioning algorithm to reduce the complexity of operations. The behavioral simulation and the implementation of the hardware circuit are completed in this paper. The experimental results based on the analog front-end and the field programmable gate array (FPGA) show that when the pulse amplitude modulation 4 (PAM4) bit rate is 12 ∼ 56Gbps and the channel loss is -5dB ∼ -17dB@14GHz, the detection BERs of 32x4 parallel ARSSDs are reduced by two orders of magnitude compared to the conventional decision feedback equalization, which is consistent with the results of the behavioral simulation.

The limitations of traditional von Neumann architectures and digital computing are the bottlenecks for high-speed signal processing capabilities, not to mention the explosion of information growth. To tackle this challenge, this paper proposes an artificial neural network (ANN) equalizer based on the memristor for high-speed channel transmission at 112Gbps with 4-level pulse amplitude modulation (PAM4). To implement the PAM4 signal decision circuit based on the softmax algorithm, a comparator is used to make binary decisions for each output, and the only high-level output is further selected for the decision-making. The simulations on the PSPICE platform reveal that the number of input taps and the location of the main tap have the greatest impact on bit error rate (BER) performance. With optimal parameters, the circuit can achieve an impressive BER performance as low as 3.45E-6. To the best of our knowledge, this is the first implementation of channel equalization using memristive circuits, providing a valuable reference for analog circuit implementations of neural network equalizers.