Shiyou Huang

dblp:187/9672 · DBLP profile ↗
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4ranked-venue papers
4as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 3 · 3 first-authorSystems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
3 papers
Concurrent programming · 35% Programming languages and type systems · 22% Program verification · 19%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Programming languages and type systems › language-based security
memory safety
0.412019
SafeCheck: safety enhancement of Java unsafe API · ICSE 2019
Debugging and program repair
bug reproduction
0.312017
Towards Production-Run Heisenbugs Reproduction on Commercial Hardware · USENIX ATC 2017
Concurrent programming
memory models
0.212016
Maximal causality reduction for TSO and PSO · OOPSLA 2016
Program verification › model checking
stateless model checking
0.212016
Maximal causality reduction for TSO and PSO · OOPSLA 2016
Concurrent programming › memory models › weak memory models
TSO and PSO
0.212016
Maximal causality reduction for TSO and PSO · OOPSLA 2016
Runtime systems and virtual machines › virtual machine implementation
java virtual machine
0.112019
SafeCheck: safety enhancement of Java unsafe API · ICSE 2019
Concurrent programming › concurrency bugs
concurrency bug reproduction
0.112017
Towards Production-Run Heisenbugs Reproduction on Commercial Hardware · USENIX ATC 2017
Program verification › model checking › partial order reduction
dynamic partial order reduction
0.112016
Maximal causality reduction for TSO and PSO · OOPSLA 2016

Methods — techniques the papers use, named apart from their topics

memory checking · 0.4bytecode instrumentation · 0.4first-order logical constraints · 0.2SMT solving · 0.2
YearPublicationVenuePosition
2019 SafeCheck: safety enhancement of Java unsafe API
abstract
Java is a safe programming language by providing bytecode verification and enforcing memory protection. For instance, programmers cannot directly access the memory but have to use object references. Yet, the Java runtime provides an Unsafe API as a backdoor for the developers to access the low- level system code. Whereas the Unsafe API is designed to be used by the Java core library, a growing community of third-party libraries use it to achieve high performance. The Unsafe API is powerful, but dangerous, which leads to data corruption, resource leaks and difficult-to-diagnose JVM crash if used improperly. In this work, we study the Unsafe crash patterns and propose a memory checker to enforce memory safety, thus avoiding the JVM crash caused by the misuse of the Unsafe API at the bytecode level. We evaluate our technique on real crash cases from the openJDK bug system and real-world applications from AJDK. Our tool reduces the efforts from several days to a few minutes for the developers to diagnose the Unsafe related crashes. We also evaluate the runtime overhead of our tool on projects using intensive Unsafe operations, and the result shows that our tool causes a negligible perturbation to the execution of the applications.
Shiyou Huang, Jianmei Guo, Sanhong Li, Yumin Qi, Kingsum Chow, Jeff Huang 0001
ICSE1
2017 Speeding Up Maximal Causality Reduction with Static Dependency Analysis
abstract
Stateless Model Checking (SMC) offers a powerful approach to verifying multithreaded programs but suffers from the state-space explosion problem caused by the huge thread interleaving space. The pioneering reduction technique Partial Order Reduction (POR) mitigates this problem by pruning equivalent interleavings from the state space. However, limited by the happens-before relation, POR still explores redundant executions. The recent advance, Maximal Causality Reduction (MCR), shows a promising performance improvement over the existing reduction techniques, but it has to construct complicated constraints to ensure the feasibility of the derived execution due to the lack of dependency information. In this work, we present a new technique, which extends MCR with static analysis to reduce the size of the constraints, thus speeding up the exploration of the state space. We also address the redundancy problem caused by the use of static analysis. We capture the dependency between a read and a later event e in the trace from the system dependency graph and identify those reads that e is not control dependent on. Our approach then ignores the constraints over such reads to reduce the complexity of the constraints. The experimental results show that compared to MCR, the number of the constraints and the solving time by our approach are averagely reduced by 31.6% and 27.8%, respectively.
Shiyou Huang, Jeff Huang 0001
ECOOP1
2017 Towards Production-Run Heisenbugs Reproduction on Commercial Hardware
Shiyou Huang, Bowen Cai 0006, Jeff Huang 0001
USENIX ATC1
2016 Maximal causality reduction for TSO and PSO
abstract
Verifying concurrent programs is challenging due to the exponentially large thread interleaving space. The problem is exacerbated by relaxed memory models such as Total Store Order (TSO) and Partial Store Order (PSO) which further explode the interleaving space by reordering instructions. A recent advance, Maximal Causality Reduction (MCR), has shown great promise to improve verification effectiveness by maximally reducing redundant explorations. However, the original MCR only works for the Sequential Consistency (SC) memory model, but not for TSO and PSO. In this paper, we develop novel extensions to MCR by solving two key problems under TSO and PSO: 1) generating interleavings that can reach new states by encoding the operational semantics of TSO and PSO with first-order logical constraints and solving them with SMT solvers, and 2) enforcing TSO and PSO interleavings by developing novel replay algorithms that allow executions out of the program order. We show that our approach successfully enables MCR to effectively explore TSO and PSO interleavings. We have compared our approach with a recent Dynamic Partial Order Reduction (DPOR) algorithm for TSO and PSO and a SAT-based stateless model checking approach. Our results show that our approach is much more effective than the other approaches for both state-space exploration and bug finding – on average it explores 5-10X fewer executions and finds many bugs that the other tools cannot find.
Shiyou Huang, Jeff Huang 0001
OOPSLA1