William Floyd-Jones

dblp:188/1126 · also Will Floyd-Jones · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 67% Reconfigurable computing and FPGAs · 33%
Artificial intelligence
1 paper
Motion planning and robot control · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA prototyping
0.212016
The microarchitecture of a real-time robot motion planning accelerator · MICRO 2016
Hardware accelerators and domain-specific architectures › robotics accelerator
motion planning accelerator
0.212016
The microarchitecture of a real-time robot motion planning accelerator · MICRO 2016
Hardware accelerators and domain-specific architectures
robotics accelerator
0.212016
The microarchitecture of a real-time robot motion planning accelerator · MICRO 2016
Robotics › Motion planning and robot control
motion planning
0.112016
The microarchitecture of a real-time robot motion planning accelerator · MICRO 2016

Methods — techniques the papers use, named apart from their topics

parallelization · 0.5hardware-software co-design · 0.5
YearPublicationVenuePosition
2019 A Programmable Architecture for Robot Motion Planning Acceleration
abstract
We have designed a programmable architecture to accelerate collision detection and graph search, two of the principal components of robotic motion planning. The programmability enables the architecture to be applied to a wide range of different robots and motion planning applications. We present the architecture of our accelerator and describe and evaluate its microarchitecture implementation.
Sean Murray, William Floyd-Jones, George Dimitri Konidaris, Daniel J. Sorin
ASAP2
2016 The microarchitecture of a real-time robot motion planning accelerator
abstract
We have developed a hardware accelerator for motion planning, a critical operation in robotics. In this paper, we present the microarchitecture of our accelerator and describe a prototype implementation on an FPGA. We experimentally show that the accelerator improves performance by three orders of magnitude and improves power consumption by more than one order of magnitude. These gains are achieved through careful hardware/software co-design. We modify conventional motion planning algorithms to aggressively precompute collision data, as well as implement a microarchitecture that leverages the parallelism present in the problem.
Sean Murray, William Floyd-Jones, George Dimitri Konidaris, Daniel J. Sorin
MICRO2