In this study, a highly efficient 6.78-MHz power amplifier (PA) is proposed for power and data transfer in implantable medical systems. Based on a soft-switching push-pull topology, the amplifier maintains high power transfer efficiency (PTE) over a wide range of resistive load without requiring compensation networks. Moreover, the PTE degradation caused by increased distance has been significantly mitigated. A programmable bus voltage enables linear control of the PA’s output power which is preferable for closed-loop power control applications. The proposed power transfer system achieves a remarkable PTE of 60.9 % at 6.78 MHz, with an output power programmable between 20 mW and 130 mW. Additionally, 100-kbps on-off keying (OOK) modulation is demonstrated to establish the forward data link of the wireless system.

The wireless clock and data may experience significant discontinuation in battery-less medical implant applications. The rise of closed-loop treatment requires the communication link to set up swiftly. To address these issues, a single-loop digital clock and data recovery (CDR) circuit based on a self-adaptive bang-bang phase and frequency detector (PFD) is proposed. For a data rate at 5 kbps, the CDR features a 4-Hz loop-bandwidth and fast locking less than 1000 cycles. A wide frequency capture range from −63% to +56% has been achieved without the need for crystal references. The CDR is realized in a digital design eliminating any off-chip components. It occupies 0.027 mm2and consumes a power consumption of 4.89 μW in a 180-nm CMOS technology. The compact form factor especially favors size-constraint medical implant applications.

Miniaturized implantable stimulation systems are of great significance in the treatment of cardiac and neurological diseases. This paper presents a high-voltage wireless power management unit (WPMU) for battery-less stimulation systems, which features only one off-chip capacitor and compatibility with low-voltage CMOS technology. A 21-stage differentially driven rectifier is employed to generate a 9-V high-voltage supply. The bandgap reference and capless LDOs are realized in a transistor-stacking topology, which not only directly operate under high-voltage supplies, but also achieve remarkable power supply rejection performances. The IC is fabricated in an 180-nm standard CMOS technology. Measurement results show the maximum power conversion efficiency to be 74.2%. The power supply of the bandgap reference and the LDOs ranges from 7.8 V to 10 V and the power supply rejection ratio (PSRR) reaches 80.6 dB.

Electrical neuromodulation has shown superior therapeutic outcomes compared with pharmacological interventions alone. This work introduces a 16-channel neurostimulation IC featuring transistor-stacked monopolar stimulation drivers in standard CMOS technology. With a self-adaptive biasing scheme, the stimulation driver ensures operational safety across all load conditions under the ±6-V voltage compliance and successfully addresses potential leakage issues in prior work. Each driver features 8-bit current control with 1 μA resolution. An on-chip charge-pump system generates ±6-V supplies using a novel multiple-output pulse-skipping modulation scheme and achieves a remarkable power density of 25.44 mW/mm2through the systematic optimization of sub-converters. The 16-channel neurostimulation IC is fabricated in a 180-nm standard CMOS technology, occupying a total pad-included area of 3 mm2. The compactness and process compatibility of the design demonstrate the potential for enabling next-generation high-channel-count neural interfaces.

This work presents an ultralow-power heart-rate system-on-a-chip (HR-SoC) for long-term continuous cardiac monitoring applications. A modified QRS-complex detection algorithm, verified on the MIT-BIH arrhythmia database, achieves a sensitivity (SE) of 99.99%, a positive predictive rate (PPR) of 99.68%, and an accuracy (ACC) of 99.68% while significantly reducing the power consumption compared to the conventional Pan-Tompkins algorithm. The system outputs averaged HRs (AHRs) and operates in an interrupt-driven architecture, dramatically saving memory resources and power consumption. The HR-SoC integrates an analog front end (AFE) for electrocardiograph (ECG) recording and a digital signal processing (DSP) back end for QRS detection, storage, and system scheduling and configuration. The AFE strikes a compromise among noise, linearity, and power consumption. Fabricated in 0.18-$\mu $m CMOS technology, the HR-SoC features a compact area of 1.55 mm2. When operating at a 1-V power supply, it consumes only$1.28~\mu $W in the AHR monitoring mode, with$0.48~\mu $W consumed by the AFE and$0.8~\mu $W by the DSP back end.

Next generation of brain-computer interface (BCI) aspires to achieve accurate and real-time spike sorting while being power--efficient. To achieve on-chip high-channel-count neural signal processing, accurate and hardware-efficient algorithms are critical. This work proposes a spike-sorting system that includes a NEO spike detector with an automatic threshold trainer, spike alignment and a feature extractor based on the first-and-second-derivative (FSDE) algorithm. The system employs a time-interleaving structure to reuse the logic cells, thus reducing the area and leakage power. The proposed system is implemented in ASIC in both 65 nm and 180 nm CMOS technologies with different folding ratios, and the product of power and area is optimized when a DSP core interleaves 8 channels. The implemented design in a 65-nm technology occupies 2.69 × 10-3mm2/channel and consumes 0.52μW/channel at a 1.2-V supply. The accuracy simulations show that the proposed NEO (δ= 1) and FSDE algorithms achieve the average spike-detection accuracy of 97.1% and clustering accuracy of 91.6%, respectively.

Pseudo-resistors are employed as substitutes for poly resistors in scenarios necessitating exceedingly high resistance values. This paper presents the design of a tunable hundreds-GΩ pseudo-resistor achieving 6.26% relative standard deviation in a 180-nm CMOS technology. The pseudo-resistor is used as a feedback resistor in a capacitively-coupled instrumentation amplifier to realize sub-Hz high-pass corners. A self-biased current source along with a dedicated pico-ampere-level current mirror DAC is employed for tuning the pseudo-resistor. The proposed current mirror DAC design reduces the impact of unwanted leakage currents to achieve improved tuning accuracy. Measurement results show that the achieved resistances are linearly dependent on the control code with a span from 230 GΩ to 845 GΩ. The capacitively-coupled instrumentation amplifier with the proposed pseudo-resistor technology is successfully tested in a Lewis-lead ECG recording experiment.

This paper presents a 10-bit 3.84-MS/s ping-pong interleaving successive approximation register (SAR) ADC designed for a 96-channel neural signal acquisition system. The ADC incorporates an input buffer and peripheral circuits which allow it to directly connect the front-end array. A ping-pong interleaving structure is adopted to double the sampling rate at a given SPI clock frequency while minimizing the power consumption of the input buffer. Unlike conventional time-interleaved ADCs, the proposed technology does not suffer from any mismatches among sub-ADCs. The ADC is fabricated in a 0.18-μm CMOS technology. It achieves an effective-number-of-bit (ENOB) of 9.45-bits at a 3.84-MS/s sampling rate with a perchannel power consumption of 17.5 μW. This work achieves the highest figure-of-merit (FOM) among literatures on multi-channel signal acquisition systems.

A prevailing trend in brain-computer interface (BCI) systems is expanding the number of recording channels to the realm of thousands. The massive quantities of raw data impose substantial demands on the data transmission bandwidth, leading to increased power consumption and thermal dissipation within implanted systems. In response to these challenges, this article proposes a stationary wavelet based Teager energy operator (SWTTEO) spike detection algorithm with adaptive thresholding, which dramatically compresses the data bandwidth. The algorithm facilitates spike detection with an accuracy exceeding 97% even under circumstances with the noise level as high as 0.2. The lifting scheme of the db3 wavelet is employed to reduce the hardware resource. The proposed spike detector for multi-channel neural interface is implemented in 65-nm and 180-nm CMOS technologies in a channel-interleaved architecture. The optimized 65-nm implementation consumes a power of 1.07 μW and an area of 4048 μm2for each channel.