Zhicong Luo

dblp:188/4632 · DBLP profile ↗
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9ranked-venue papers
0as first author
9since 2021 · last 2026
0000-0001-6008-3897ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 6 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
YearPublicationVenuePosition
2026 Transformer-based surrogate modeling for multi-circuit analog sizing via Bayesian optimization
Wuwei Chen, Xiaogan Li, Jinghu Li 0001, Zhicong Luo
Integr.6
2026 Semantic segmentation of power equipment guided by multi-modal and multi-level wavelet for UAV inspections
Jianshu Chao, Ruoyun Liu, Deyu An, Bangjiang Lin, Dapeng Ye, Zhicong Luo
Pattern Recognit.8
2026 A High Efficiency Dual Mode Buck Converter With a Novel Seamless and Fast Transition Scheme
abstract
This paper presents a high-efficiency dual-mode off-time controlled buck converter with a novel seamless and fast mode transition scheme. The proposed seamless fast mode transition (SFMT) technique employs a mode selector consisting of a voltage detector (VD) and ripple-to-digital conversion circuit (RDC), solving the prolonged frequency transition problem in conventional mode-switching methods. Additionally, the introduced dynamic sleep clock management adaptively disables idle circuits based on duty cycle variations, achieving high efficiency across wide load ranges. Implemented in 0.18-$\mu $m technology, the converter occupies$0.5525~mm^{2}$while operating from a 2.5-3.6 V input to deliver 1.2 V output. Measurement results demonstrate$93.7~\%$peak efficiency at 0.4 A load and$80.5~\%$high light-load efficiency at 1 mA. The design achieves$\mu $s slew rate) with 28-$\mu $s recovery time, while maintaining low output ripple. Compared with reported designs, the proposed buck converter achieves an outstanding figure-of-merit ($FoM_{1}$) of$7.26~\mu s/(A^{2}/mm^{2})$.
Yun Chen 0001, Jinghu Li 0001, Zhicong Luo
IEEE Trans. Circuits Syst. I Regul. Pap.7
2025 ChebSpec-Net: Linear Spectral Graph Restoration for UHD Images
Xin Su 0009, Zhuoran Zheng, Jianshu Chao, Dapeng Ye, Zhicong Luo
PRCV (8)5
2024 EEG-based Epilepsy Detection Using Robust Feature Learning Model with Manhattan Distance and L1 Regularization
abstract
The automatic detection of epilepsy based on electroencephalography (EEG) has been proven effective under feature learning models. However, the practical implementation often encounters challenges from noise contamination presented in EEG signals. To address issues related to noise interference, we proposed a robust feature learning model for EEG-based epilepsy detection using Manhattan distance and L1 regularization. Specifically, we introduced Manhattan distance to construct the weight of the L1 regularization term in LASSO and obtained epilepsy-related information in the spectrum components of the original EEG signals and the differentiated signals through the LASSO-based feature selection. We verified the performance of our proposed model using the public EEG dataset. The model achieved the best performance, outperforming competing models. In addition, we tested the performance under noise interference by simulating EEG signal noise, indicating that our model is robust in EEG-based epilepsy detection.
Weihai Huang, Weize Yang, Zhicong Luo, Jun Qi 0001, Qiyan Sun, Xiangzeng Kong
BIBM3
2024 Sound-based Bee Colony State Analysis Using Compact MFCC Patterns
abstract
Bees play an important role in agricultural production. However, beekeeping relies on experienced beekeepers to take time and effort to maintain the bee colonies. To lower the threshold of beekeeping and improve efficiency, we proposed a sound-based bee colony state analysis model using compact Mel frequency cepstral coefficient (MFCC) patterns. Facing high-dimensional bee colony sound signals, we obtained MFCCs from the signals and constructed a set of filters to extract MFCC-based compact features called compact MFCC patterns. After extracting compact features, the feature set was given to the support vector machine classifier. We recorded the sounds of bee colonies under normal conditions and in the absence of the queen bee to verify the proposed model. While significantly compressing the dimensionality of MFCCs, the model still achieved an accuracy score of 99.30% in distinguishing the presence of the queen bee. The extracted compact MFCC patterns effectively and compactly characterize the information related to the bee colony states in the bee colony sound signals, giving the model an excellent ability to discriminate the state of the bee colony.
Weihai Huang, Weize Yang, Zhicong Luo, Jun Qi 0001, Xiangzeng Kong
ISPA3
2024 A 10-Gb/s low-power inverter-based optical receiver front-end in 0.13-μm CMOS process
Yihong Gong, Ruiyong Tu, Sini Wu, Qiyan Sun, Jinghu Li 0001, Zhicong Luo
Integr.8
2024 A rail-to-rail high speed comparator with LVDS output in 0.18-μm SiGe BiCMOS Technology
Qiyan Sun, Ruiyong Tu, Yihong Gong, Sini Wu, Jinghu Li 0001, Zhicong Luo
Integr.7
2023 A 10-Gb/s Inductorless Low-Power TIA With a 400-fF Low-Speed Avalanche Photodiode Realized in CMOS Process
abstract
Compared with SiGe technology, the limits of low transition frequency and low transconductance per unit current of CMOS technology result in poor noise, narrow bandwidth, and high power consumption in high-speed transimpedance amplifiers. The aforementioned issues are further exacerbated while using a low-speed low-cost photodiode. In this study, an equalization technique is proposed to increase the feedback resistance$\boldsymbol {R_{F}}$, achieving low noise and bandwidth extension of the chip. A novel inductorless bandwidth extension technique is proposed to increase the bandwidth of high-speed channel by 37.5%. In addition, a new current reuse technique is proposed to inject the output stage’s tail current into the input stage to achieve a high gain, saving power consumption by 20%. We achieve 10-Gb/s operation with a 400-fF avalanche photodiode (APD) using 65-nm CMOS technology. The bandwidth is 6.8 GHz, the transimpedance gain is 66 dB$\boldsymbol{\Omega }$, the average input-referred noise current is 11.9 pA/$\surd $Hz, and the average sensitivity is −22.4 dBm at a BER of 1e−12. The SF-TIA chip takes up 0.56 mm2 and consumes 26 mA from a 3.3-V supply.
Haofan Ding, Haiyan Dai, Deyan Chen, Junyuan Wu, Jinghu Li 0001, Zhicong Luo
IEEE Trans. Very Large Scale Integr. Syst.7