This paper presents an overview of the Internet of Things (IoT) device design and simulation, with a specific focus on low-power design principles - everything in the context of the LoLiPoP-IoT project. The project aims to enhance IoT device usability by reducing maintenance requirements related to battery recharging or replacement. Another key goal is to significantly decrease the massive waste generated by discarded primary batteries, contributing to more sustainable and user-friendly IoT solutions for the future. The primary focus of this paper is on a custom IoT localization tag, for which we simulate solar cells - ranging from basic modeling to their integration into electrical circuits - and the power consumption of the tag's electronics platform. The analyzed sample platform is built on the nRF52833 microcontroller and the DW3110 ultra-wideband transceiver. We also applied our experimental framework principles to optimize power consumption and extend battery life. Reductions in photovoltaic panel area were achieved for both devices with a 5-year lifespan and fully autonomous tags, though with increased localization latency. Furthermore, this paper demonstrates how IoT devices, including their firmware, can be effectively modeled and simulated using publicly available tools.

The increasing interest in IoT devices poses significant challenges in battery waste, not to mention the effort needed to replace the batteries in remote applications. In the LoLiPoPIoT project, we address these issues by developing energy-efficient IoT platforms that extend the device’s battery life through lowpower design and energy harvesting. However, for a successful design, preliminary measurements and simulations need to be done to demonstrate the feasibility of the utilized technologies and their dimensioning. This paper presents a method of collecting data and creating a novel portable simulation model implemented in a Microsoft Excel spreadsheet. During the data collection phase, we plot detailed energy consumption and income of our device (i.e., asset tracking tag). PC1D simulations of a crystalline-silicon photo-voltaic panel and the device model were utilized to collect data for the final (i.e., composed) model. Our model allows real-time adjustments of key parameters, such as ambient light intensity, battery capacity, and photo-voltaic panel sizing. Our goal is to deliver a solution that allows our partner to conduct basic experiments on their own computers with a user-friendly interface for parameter selection and result visualization. Our results indicate that for one application area, a $25 \mathrm{~cm}^{2}$ photovoltaic panel is needed, while for the other, a $23 \mathrm{~cm}^{2}$ panel is enough.

The LoLiPoP-IoT project aims to pioneer Long Life Power Platforms for IoT to extend battery life, minimize maintenance, and facilitate installation within existing environments. With a focus on supporting an inclusive ecosystem of developers, integrators, coordinators, and users, the project's Grand Objectives encompass a range of aims, including providing long-lasting battery solutions, reducing battery waste, enhancing asset tracking and predictive maintenance, and improving energy efficiency in buildings. These objectives are realized through nine selected practical applications across three primary domains: Asset Tracking, Condition Monitoring and Predictive Maintenance, and Energy Efficiency and Comfort in Buildings. Expected impacts of the LoLiPoP-IoT project include significantly extended battery life, reduced maintenance overhead, decreased costs associated with asset location, improved asset management efficiency, enhanced building comfort with reduced energy consumption, and substantial revenue generation for industry partners. The project's strategic objectives are notably harmonized with key EU initiatives outlined in the Green Deal, Circular Economy, and the New Industrial Strategy for Europe.

This paper presents and evaluates the possibility of automatic design of fault-tolerant systems from unhardened systems. We present an overview of our toolkit with its three main components: 1) fault-tolerant structures insertion (which we call helpers); 2) fault-tolerant structures selection (called guiders); and 3) automatic testbed generation, incorporating advanced acceleration techniques to accelerate the test and evaluation. Our approach is targeting complete independence on the HW description language and its abstraction level, however, for our case study, we focus on VHDL in combination with fine-grained n-modular redundancy. In the case study part of this paper, we proved that it is undoubtedly beneficial to select a proper fault tolerance method for each partition separately. Three experimental systems were developed with the usage of our method. Two of them achieved better reliability parameter while even lowering their chip area, compared to static allocation of equivalent fault tolerance technique type. In the case study, we target the best median time to failure, the so-called t50, however, our method is not dependent on this parameter and arbitrary optimization target can be selected, as soon as it is measurable.

A computing power is important in space applications where a utilization of FPGAs is very useful. However, the FPGAs are susceptible to manifestations of radiation which can cause malfunction. Particularly dangerous are configuration memory faults known as Single Event Upsets (SEUs), which can lead to the entire system failure. Therefore, the fault-tolerant techniques are used to prevent system failures. The main motivation for the use of these techniques is to maintain the correct behavior of the system despite the occurrence of faults. In addition to fault masking, which only delays system failures due to fault accumulation, the utilization of fault mitigation by partial dynamic reconfiguration was used. Everything needed is provided by the reconfiguration controller, which is a necessary additional component of the entire system. It is also very convenient to be able to detect the occurrence of fault in the system. After that, the system need not be restored unnecessarily, which saves useless work of the controller. The aim is to evaluate the benefit of reconfiguring damaged parts of the system to increase fault tolerance. In all experiments, an experimental platform was used that emulates an electromechanical system, which consists of a robot control unit on an FPGA and a simulation of their behavior on a PC. Artificial faults have been injected into the FPGA configuration memory that corresponds to this controller.

This paper evaluates the practical usage of the Multiple-choice Knapsack Problem (MCKP) solver to automatically select the proper fault mitigation method for each component to maximize the overall fault tolerance of the whole system. The usage of the MCKP is placed into the context with our fault tolerance automation toolkit, the goal of which is to completely automate the process of fault-tolerant system design on a very general level. To achieve our goal, we present our research on Field Programmable Gate Arrays (FPGAs) for which we have developed the specific components in order to support their fault-tolerant design automation. In our particular case study, the MCKP method on the partitioned system was able to find the solution with 18% less critical bits compared to our previous approach, while even lowering the circuit size. The results indicate that by splitting the system into smaller components and applying the MCKP method, considerably better results in terms of critical bits representation can be achieved.

In this research paper, analysis of smart electronic lock behavior during presence of faults in its controller is examined. A typical smart electronic lock is composed of a controller unit, usually implemented in a processor, and the mechanical part, which may be for example a stepper motor. The goal of this research paper is to examine the consequences of failing controller running a partly hardened program, which we developed from the experiences we gained in our previous research. We implement the controller processor in Field Programmable Gate Array (FPGA) in order to inject faults into our components. This paper focuses on fault injection into occupied parts of Instruction Memory (IMEM) and Data Memory (DMEM). Moreover, permanent failures of the processor are simulated by fault injection into occupied Look-up Tables (LUTs) of the processor design on the FPGA. Our results show that the application of certain SW-implemented fault tolerance methods may, in opposite, degrade the hardness of the system. Our experiments imply that the IMEM is the most sensitive to fault injection, because there is no possibility for an eventual self repair. In the case of DMEM, erroneous values may be possibly repaired when the variable is rewritten back to the memory, slightly lowering the DMEM sensitivity to fault injections. The CPU itself is the least susceptible. Although faults are injected to the utilized contents only, for the CPU LUTs, a certain part of the logic may not be used to implement the required function.

This research paper presents an analysis of electronic smart locks and explores the influences of faults on its controller unit. Electronic smart locks often utilize stepper motor as an actuator. Stepper motors, however, need a controller, which is usually implemented in a processor. The aim of our research is to examine the consequences of a failing controller processor. In our previous research, we developed a platform for fault tolerance testing with the ability to monitor the impacts on the mechanical part. We also developed a framework for accelerated testing of fault tolerance properties. The processor can be implemented in an FPGA (Field Programmable Gate Array) in order to be able to emulate HW faults inside the processor. In this paper, the concept of testing a smart lock is presented alongside with the first experimental results utilizing the direct generation of invalid stimuli for the stepper motor. In our research, we found out that random errors probably could not be used for an unauthorized unlock, especially if the lock utilizes a mechanical gearbox. Deeper logic and knowledge of the correct sequence of steps used by the selected motor are needed to perform an attack to unlock the lock. On the other hand, random sequences could cause that lock not to be locked by falsifying the lock request sequence. The second interesting fact is that x% of faults in the valid sequence give the same rotation angle as (100-x)% of faults.

The complexity of today's systems is growing along with the level of chip integration. This results in higher demand for reliability techniques; it also increases the difficulty of incorporating reliability in such systems. For this purpose, we are working on a method to automate reliability insertion; however, for this method, it is necessary to have feedback on the result. In this paper, one component of the automation flow enabling the estimation of the resulting reliability - Fault Tolerance ESTimation (FT-EST) framework - is presented along with an improvement for accelerating the time necessary to reach the estimation. For the purpose of evaluation, we are using our Redundant Data Types approach, which enables us to intentionally insert reliability in a particular operation. The estimation utilizes the concept of fault injection. The results indicate, that the concept of Redundant Data Types is functional, however, also suggest its future improvements (e.g. for the operation of subtraction).

Various electronic systems play an important role in our everyday lives. Some of them serve for fun or to make our lives easier. These systems are useful but not necessary; when they malfunction, the consequences are not critical. On the other hand, there are systems which are more or less critical, and their failure can cause undesirable consequences. For example, a failure in medicine, aviation, the army or automotive systems can cause high economic losses and/or endanger human health. These systems must be protected against the impact of faults, and flawless operation must be ensured. Fault tolerance is one of the techniques that will ensure this. There are many fault-tolerance methodologies targeted towards various systems and technologies, and new methodologies are being investigated. It is also important to verify these techniques; this is the main topic of this paper. An evaluation platform for testing fault-tolerance methodologies targeted towards SRAM-based FPGAs (Field Programmable Gate Arrays) is presented and demonstrated. A robot for seeking a path through a maze and the processor-based robot controller serve as an experimental system case study. Experimental results with the unhardened and hardened versions of the processor-based robot controller are presented and discussed.

Faults occurring in the safety-critical systems can lead to the failure of the whole system and cause high economical losses or endanger human health. As an example, space, aerospace or medical systems which are working in the environment with increased occurrence of faults can serve. Fault avoidance and fault tolerance are the main techniques, the goal of which is to avoid such situations. This paper is the continuation of the previously published work and presents an approach to evaluate fault tolerance techniques by monitoring the impact of faults in the experimental electro-mechanical system which consists of the robot in a maze and its robot controller. The experiments with the robot controller hardened against faults are combined with the reliability analysis on a theoretical level in this paper. The impact of faults artificially injected into the robot controller, in which Triple Modular Redundancy is applied, is monitored and used for statistic reliability analysis.

Functional verification is a modern approach to verifying that a digital system complies with its specification. The verification environment for functional verification of robot controller which searches path for the robot through a maze is presented in this paper. This verification environment is designed according to UVM (Universal Verification Methodology) principles. As an interesting feature of the verification environment we see the use of a mechanical part (robot in a maze) simulation. The article describes the use of the verification environment for evaluating impacts of faults in electro-mechanical systems. It will serve as a tool for automating the fault tolerance evaluation of electro-mechanical systems and together with the fault injector will form the basis of the verification platform in the future. The experimental results gained from the verification process are also presented in the paper.

This paper presents concepts of FPNN which can be used for the implementation of artificial neural networks in FPGAs and introduces fault tolerant techniques applied on this concept that are developed by the authors.

This paper presents an approach to fault-tolerant systems design and synthesis based on High-level Synthesis (HLS). A description and evaluation of the impacts of HLS optimization methods are shown as well. The higher reliability is achieved through modification of input description in the C++ programming language on which the HLS synthesis tools are based on. Our work targets SRAM-based FPGAs, which are prone to Single Event Upsets (SEUs). For the evaluation of impacts of HLS optimization methods we use our evaluation platform, which allows us to test fault tolerance properties of the Design Under Test (DUT). The evaluation platform is based on functional verification combined with fault injection.

The aim of this paper is to present a new platform for evaluating impact of faults on electro-mechanical systems based on SRAM-based FPGAs. Functional verification together with the fault injector serve as a tool for the fault tolerance evaluation. The article demonstrates the use of the verification environment for evaluating impacts of faults in electro-mechanical systems. Our system consists of mechanical robot and its electronic controller implemented into FPGA. The experimental results gained from the verification process are also presented and discussed in the paper.