Ferroelectric FET (FeFET)-based arrays are promising candidates for energy-efficient, high-density non-volatile memory in data-intensive applications. However, charge-trappinginduced degradation and process variations pose significant reliability challenges. These effects lead to reduced memory window and degraded read accuracy over time. We propose a workload-aware degradation modeling and readout framework for FeFET arrays. First, we select a small set of representative workloads to efficiently capture degradation trends across a large workload space. We apply a two-step method to reduce read error: (a) adjust intermediate state currents to widen the separation between states; (b) select optimum reference thresholds based on the shifted distributions. Next, we perform detailed tradeoff analysis involving degradation improvement, on-chip area, and the overhead of a memory-mapped CPU polling system for in-field workload tracking. This is the first work to propose adaptive reference prediction for FeFETs based on runtime workload characteristics. Our framework improves read reliability with minimum hardware overhead and enables scalable in-field monitoring for future FeFET-based systems.

Ferroelectric field-effect transistors (FeFETs) have many promising applications, but the impact of manufacturing imperfections on these devices has yet to be studied comprehensively. We extend a previous FeFET compact model to combine the Preisach ferroelectric capacitor model with the BSIM-SOI MOSFET model. We calibrate this new compact model with data from a technology CAD model that is calibrated against a fabricated metal-ferroelectric-metal capacitor. We analyze polarization defects in the ferroelectric layer using this compact model. We address two classes of defects and map them to stuck-at-fault models, referred to as neutral faults, and stuck-at-plus and stuck-at-minus faults. We also present an analysis of the impact of device-level opens, shorts, coupling faults and extrinsic variations on the multi-level FeFET device in a 1T-1FeFET cell. Simulation results under a clustered fault distribution with a 2% fault rate for faults show a maximum accuracy degradation of 83.86% and 81.66% for ResNet18 and VGG16, respectively when inferencing is performed on faulty FeFET crossbar designs. Similarly, extrinsic variations and clustered polarization defects show a maximum accuracy degradation of 80% and 75% across both DNN models, respectively. We also evaluate the effectiveness of write-verify for mitigating the impact of extrinsic variations, polarization defects, and BEOL faults.

Warpage is a major concern in fan-out wafer-level packaging (FOWLP) due to the complex thermal processing steps involved in manufacturing. These steps include curing, electroplating, and deposition, which induce residual stresses through differential thermal expansion and contraction of materials. This effect is further amplified by mismatches in the coefficients of thermal expansion (CTE) between different materials. In particular, high-density interconnects in the back-end of line (BEOL), redistribution layers (RDLs), and through-mold vias (TMVs) are susceptible to warpage-induced stress, strain, and deformation. This work conducts structural simulations to analyze warpage in the BEOL stack induced by FOWLP. Our results indicate that the impact of warpage is non-uniform across the entire BEOL geometry of a die, hence it impacts different metal layers differently, and different coordinates within one metal layer differently. We leverage this warpage analysis to calculate parasitics and evaluate the resulting changes in path delays.

Advanced packaging technologies are reshaping; semiconductor integration, offering unprecedented improvements in performance, efficiency, and miniaturization. Among these Fan-Out Wafer-Level Packaging (FOWLP) has emerged as a transformative solution, pushing the limits of chiplet integration through its superior electrical performance, reduced footprint, and enhanced thermal management However, FOWLP presents several challenges, including coefficient of thermal expansion mismatch, warpage, die shift, and post-molding protrusion, all of which can lead to misalignment and defects. Moreover, thermo-mechanical stresses in the organic package induce warpage and delamination, further exacerbating weak defects during runtime operation. To address these challenges, we propose a comprehensive defect analysis and testing framework for FOWLP interconnects. Defects are mapped to equivalent electrical circuit models, allowing for precise fault characterization. A built-in self-test (BIST) architecture is introduced to detect open and bridging faults while accurately diagnosing fault types and localizing them. An embedded ring oscillator within the BIST network detects weak opens, bridging and coupling faults, quantifying the size of the defects. We demonstrate how this test framework can be utilized at different supply voltage corners and for various transistor sizes to reduce fault-effect aliasing due to process variations, thereby ensuring robust diagnostics, yield learning, and silicon lifecycle management. The effectiveness of the ring oscillator circuit is validated through HSPICE simulations using equivalent faulty circuit models for a 7 nm CMOS technology.

Fan-out wafer-level packaging enables heterogeneous chiplet integration via Cu pillars and redistribution layers (RDLs). As FOWLP technology evolves, the focus is shifting towards many-chiplet designs, necessitating multi-layer RDL structures to route interconnects between these chiplets. However, defects such as opens, shorts, and coupling are a challenge for RDL structures. High-density, multi-layer RDLs exacerbate these challenges, leading to intensified coupling, elevated switching activity, and shorts within metal segments. Moreover, the finer pitch of RDLs increases electromigration due to rising current densities. We propose a routing-aware testing framework that leverages the multi-layer RDL routing Information to target realistic shorts and coupling defects. By physically partitioning interconnects into regions, we enable test scheduling and leverage shared test-pattern generators for launching test patterns and capturing responses to reduce test time and area overhead without compromising fault coverage. The framework’s effectiveness is demonstrated on four many-chiplet package designs with varying configurations of chiplet-to-chiplet connectivity. Our results show that this method can achieve over 99.8 % fault coverage with an n-fold reduction in test area and test time through an n-way partitioning strategy.

Safety-critical applications such as autonomous driving demand rigorous functional safety assurance. We present a safety-guided test pattern generation framework called NeuralTPG for transition faults in integrated circuits (ICs) based on Launch-on-Capture (LOC) delay testing. We model the logical state transition behavior of standard cells using multilayer perceptrons (MLPs), referred to as Cell-Nets. The neural twin is constructed by converting standard cell instances into Cell-Nets and replacing inter-cell wires with neural connections. We leverage the end-to-end differentiability of the neural twin to compute input test-pattern pairs for transition faults through back-propagation. The neural twin enhances fault propagation to primary outputs (POs) and generates test-pattern pairs that maximize faults’ propagation capability. The framework supports non-binary, user-defined criticality-factor (CF) assignment across the circuit’s internal nets and POs, enabling CF-guided test-pattern pair generation to propagate transition faults to more critical POs. NeuralTPG employs concurrent test generation, fully leveraging GPU acceleration to generate test-pattern pairs for all transition faults simultaneously, thereby improving test efficiency. Experimental evaluations on six benchmarks across three CF configurations demonstrate that NeuralTPG can be used to achieve safety-guided fault propagation.

Ferroelectric Field-Effect Transistors (FeFETs) are emerging as promising candidates for non-volatile memory and in-memory computing due to their low power consumption, fast switching speeds, and high integration density. However, device-level defects and process variations pose significant challenges to their reliability, particularly for multi-level cell (MLC) FeFETs. Polarization defects in the ferroelectric layer and back-end-of-line (BEOL) defects lead to memory window reduction and erroneous computations in FeFET-based crossbars. We propose a March test solution tailored for MLC FeFETs that detects and diagnoses BEOL defects in the presence of underlying process variations and polarization defects.

With the analog defect modeling and coverage standard, IEEE P2427, coming close to being published, analog circuit testing seems poised to kick into high gear. Working backwards from the goal of lowering analog DPPM, in this talk we will present a practical workflow with emphasis on a few key components – systematic analysis of defect detectability, stimulus quality assessment, and analog test generation – and how these can be applied effectively.

Achieving optimal test coverage and quality with fewer test patterns is a persistent challenge for DFT teams. This endeavor demands expert user involvement and lengthy iterative processes to fine-tune various tool parameters specific to each design core. Additionally, optimizing the test pattern count and reducing test data volume require refining the test configuration and compression logic during design implementation. This presentation explores how AI-driven DFT solutions can optimize the number of structural test (Scan/ATPG) patterns to meet target test coverage. By integrating advanced AI techniques in ATPG pattern generation and test configuration during DFT implementation, we demonstrate significant improvements in the engineering efficiency and test cost reduction.

The proliferation of resource-intensive large language model (LLM) workloads has driven interest in consistency and reliability of their performance on mobile SOCs. Prior work on latency prediction for Deep Neural Network (DNN) execution has primarily examined training predictors for CNNs for each chip under test and requires re-training or fine-tuning to adapt to new hardware or account for variations in performance between chips. To fill this gap, we present a latency prediction framework for LLMs on mobile GPUs that allows easy adaptation to performance variation in new devices and variability-aware estimation of LLM workload latency without requiring extensive access to low-level compilation features such as Instruction-Set Architecture (ISA) information. Our approach has been tested on multiple mobile devices, achieving sub-15% error in latency prediction for multiple LLMs.

Monolithic 3D (M3D) integration for integrated circuits (ICs) offers the promise of higher performance and lower power consumption over stacked-3D ICs. However, M3D suffers from large power supply noise (PSN) in the power distribution network due to high current demand and long conduction paths from voltage sources to local receivers. Excessive switching activities during the capture cycles in at-speed delay testing exacerbate the PSN-induced voltage droop problem. Therefore, PSN reduction is necessary for M3D ICs during testing to prevent the failure of good chips on the tester (i.e., yield loss). In this paper, we first develop an analysis flow for M3D designs to compute the PSN-induced voltage droop. Based on the analysis results, we extract the test patterns that are likely to cause yield loss. Next, we propose a reinforcement learning (RL)-based framework to insert test points and generate low-switching patterns that help in mitigating PSN without degrading the test coverage. Simulation results for benchmark M3D designs demonstrate the effectiveness of the proposed power-safe testing approach, compared to baseline cases that utilize commercial tools.

Scan-obfuscation schemes used with logic locking lack the ability to perform scan authentication on a per-pattern basis. These methods are of limited effectiveness in obfuscating scan data and they remain vulnerable to SAT-based scan deobfuscation attacks. In addition, prior methods designed to perform scan-data authentication are not adequate under the strongest threat models used to assess logic locking. To alleviate these problems, we propose enhancements to TaintLock, a lightweight dynamic per-pattern authentication and encryption scheme that uses taint and signature bits embedded within each test pattern to provide authenticated scan access. To prevent IP theft through Oracle-free and Oracle-guided attacks, TaintLock is paired with truly random logic locking (TRLL). TaintLock cryptographically authenticates each test pattern using the embedded taint and signature bits and passing them through a substitution-permutation (SP) network. It further uses cryptographically generated keys to dynamically encrypt scan data for unauthenticated users. TaintLock, while offering a low overhead and nonintrusive secure scan solution may remain susceptible to a new class of Oracle-reconstruction attacks that use machine learning. Additionally, assuming test pattern security is compromised, it may be potentially vulnerable to a template-based SAT attack aimed at partial key recovery. We analyze the susceptibility of TaintLock against these threats and demonstrate its resilience. We also demonstrate that TaintLock can be easily integrated with popular test architectures, such as embedded deterministic test (EDT). Finally, we also discuss the reconfigurable nature of TaintLock’s architecture to support different levels of encryption and authentication.

Analog and mixed-signal (A/MS) integrated circuits (ICs) are crucial in modern electronics, playing key roles in signal processing, amplification, sensing, and power management. Many IC companies outsource manufacturing to third-party foundries, creating security risks such as syntactical bugs and stealthy analog Trojans. Traditional Trojan detection methods, including embedding circuit watermarks and hardware-based monitoring, impose significant area and power overheads while failing to effectively identify and localize the Trojans. To overcome these shortcomings, we present SPICED+, a software-based framework designed for syntactical bug pattern identification and the correction of Trojans in A/MS circuits, leveraging large language model (LLM)-enhanced detection. It uses LLM-aided techniques to detect, localize, and iteratively correct analog Trojans in SPICE netlists, without requiring explicit model training, and thus incurs zero area overhead. The framework leverages chain-of-thought reasoning and few-shot learning to guide the LLMs in understanding and applying anomaly detection rules, enabling accurate identification and correction of Trojan-impacted nodes. With the proposed method, we achieve an average Trojan coverage of 93.3%, average Trojan correction rate of 91.2%, and an average false-positive rate of 1.4%.

Many real-life safety-critical applications such as autonomous driving require functional safety. We present a framework for functional safety-guided test pattern generation. We incorporate the functional information of each standard cell into a multi-layer-perceptron (MLP), referred to as Cell-Net. Each Cell-Net is a pre-trained MLP that models the behavior of the corresponding standard cell. The design netlist is translated into its neural twin, where the standard cell instances are substituted by their corresponding Cell-Nets and the wires in the netlist translate to neural connections between these Cell-Nets. We leverage the neural twin-enabled back-propagation for gradient computation, and utilize these gradients to compute test patterns. The output of every Cell-Net is associated with a bias that represents a perturbation in the signal propagating through that Cell-Net. We manipulate these bias values to inject stuck-at faults at the output of Cell-Nets. We utilize the neural twin to enhance the propagation of faults to primary outputs (POs), and find the test patterns that maximize the propagation of faults to POs. The neural twin also enables the assignment of non-binary criticalityfactors (CFs) to different POs and perform a test-pattern search for each fault for a given CF configuration. Our results on five benchmark circuits across three different CF configurations show an increased fault propagation achieved by the neural twin as compared to Automatic Test Pattern Generation (ATPG).

Ferroelectric field-effect transistors (FeFETs) are a promising emerging non-volatile memory, but the impact of manufacturing imperfections on these devices has yet to be studied comprehensively. We extend a previous FeFET compact model to combine the Preisach ferroelectric capacitor model with the BSIM-SOI MOSFET model. We calibrate this new compact model with data from a technology CAD (TCAD) model that is calibrated against a fabricated metal-ferroelectric-metal capacitor. We analyze polarization defects in the ferroelectric layer using this compact model. We address two classes of defects and map them to stuck-at-fault models, referred to as neutral faults (SAP0), and stuck-at-plus and stuck-at-minus (SAP+and SAP−) faults. This framework obviates the need for computationally expensive TCAD simulations for each defect scenario.

Resistive random access memory (RRAM) constitutes a promising technology for next-generation memory architectures due to its simple structure, high on/off ratio, and processing-in-memory ability. Its compatibility with emerging monolithic 3-D (M3D) integration enables extremely high density using monolithic inter-tier vias (MIVs). However, both RRAM and M3D are susceptible to high defect rates due to immature manufacturing processes and process variations. Research efforts have been devoted to RRAM testing, while existing test solutions predominantly focus on fault detection. Fault diagnosis for M3D-integrated RRAM and MIVs remains unexplored. In this work, we propose a diagnosis procedure to identify the fault origin when a chip fails the manufacturing test. We present a detailed characterization of RRAM faulty behaviors in the presence of concurrent process variations and manufacturing defects. Based on RRAM characteristics, we develop a diagnosis sequence by identifying appropriate reference resistance and applied voltages to efficiently distinguish fault origins. Experimental results show that the proposed solution is compatible with existing test algorithms to significantly improve diagnostic resolution. By appending the proposed sequence to test algorithms, over 90% diagnostic resolution is achieved for every type of fault considered in an M3D-integrated RRAM.

Recent breakthroughs in heterogeneous integration (HI) technologies using 2.5D and 3D ICs have been key to advances in the semiconductor industry. However, heterogeneous integration has also led to several sources of distrust due to the use of third-party IP, testing, and fabrication facilities in the design and manufacturing process. Recent work on 2.5D IC security has only focused on attacks that can be mounted through rogue chiplets integrated in the design. Thus, existing solutions implement inter-chip let communication protocols that prevent unauthorized data modification and interruption in a 2.5D system. However, none of the existing solutions offer inherent security against IP theft. We develop a comprehensive threat model for 2.5D systems indicating that such systems remain vulnerable to IP theft. We present a method that prevents IP theft by obfuscating the connectivity of chiplets on the interposer using reconfigurable interconnection networks. We also evaluate the PPA impact and security offered by our proposed scheme.

Monolithic 3D (M3D) integration for integrated circuits (ICs) offers the promise of higher performance and lower power consumption over stacked-3D ICs. However, M3D suffers from large power supply noise (PSN) in the power distribution network due to high current demand and long conduction paths from voltage sources to local receivers. Excessive switching activities during the capture cycles in at-speed delay testing exacerbate the PSN-induced voltage droop problem. Therefore, PSN reduction is necessary for M3D ICs during testing to prevent the failure of good chips on the tester (i.e., yield loss). In this paper, we first develop an analysis flow for M3D designs to compute the PSN-induced voltage droop. Based on the analysis results, we extract the test patterns that are likely to cause yield loss. Next, we propose a reinforcement learning (RL)-based framework to insert test points and generate low-switching patterns that help in mitigating PSN without degrading the test coverage. Simulation results for benchmark M3D designs demonstrate the effectiveness of the proposed power-safe testing approach, compared to baseline cases that utilize commercial tools.

As Moore's Law approaches its physical limits, monolithic 3D (M3D) integration offers continued power, performance, and density improvements. However, M3D integration can lead to large power supply noise (PSN) in the power distribution network due to high current demand and long conduction paths, leading to PSN-induced voltage droop problems. The PSN-induced voltage droop is more severe for at-speed delay testing than for the functional mode. Power-safe testing is therefore essential to prevent good chips from failing on the tester (i.e., yield loss). We propose a scan cell segmentation framework to reduce power consumption during scan capture. We use reinforcement learning to insert scan cell segments that can minimize switching activity without any adverse impact on test coverage. Simulation results for benchmark M3D designs highlight the effectiveness of the proposed framework.

Emerging devices are susceptible to manufacturing defects due to immature fabrication processes. Ferroelectric field-effect transistors, referred to as FeFETs, are promising emerging devices, but the impact of manufacturing imperfections on these devices has yet to be studied. Thus, we combine a technology CAD (TCAD) model with a fault-injection technique to represent fabrication defects in a FeFET. The TCAD model is calibrated against a fabricated metal-ferroelectric-metal capacitor and uses a multi-domain ferroelectric-layer structure. We address two classes of defects in the ferroelectric layer and map them to stuck-at-fault models referred to as neutral faults (SAP°) and stuck-at-plus and stuck-at-minus (SAP+and SAP−) faults. We also develop a machine-learning (ML) framework to characterize these fault-injected FeFET devices. The ML framework provides a significant speedup in predicting the health of the FE layer as compared to computationally heavy TCAD simulations. Our study of defects in ferroelectric FET (FeFET), which is done for the first time, and the insights gained thereof can provide valuable feedback for the fabrication and yield learning of FeFET-based circuits.

We propose a black-box optimization method to generate functional test patterns for AI inferencing accelerators. Functional testing is faster than structural testing as scan chains are not used for shifting in patterns and shifting out test responses. Moreover, functional testing reduces "over-testing" by targeting the detection of functionally critical faults for a given application workload. We use Bayesian Optimization for targeted test-image generation for stuck-at faults in a systolic array-based accelerator. Our framework supports test-pattern compaction and leverages various types of error regularization for enforcing functional-likeness of the generated test images. We achieve high fault coverage using a small set of test images for pin-level faults in 16-bit and 32-bit floating-point processing elements of the systolic array achieves high fault coverage with a small set of test images.

Monolithic 3D (M3D) integration leverages fine-grained monolithic inter-tier vias (MIVs) to achieve significant improvements in power, performance, and area compared to conventional 2D integrated circuits (ICs). However, immature M3D fabrication flows lead to the degradation of device performance and unreliable interconnects between tiers. To improve yield learning, it is essential to perform fault localization at the tier level, which enables targeted diagnosis and process optimization efforts. This paper presents a graph neural network-based (GNN-based) diagnosis framework that efficiently localizes faults to a device tier and susceptible MIVs. The proposed solution offers rapid feedback to the foundry and improves the quality of diagnosis reports. The transferability of the GNN models makes it possible to perform diagnosis on designs with various design configurations without performance degradation. Results for four M3D benchmarks highlight the effectiveness of the proposed framework.

Testability and dependability (e.g., safety) of AI hardware (e.g., GPU, AI accelerators) and AI-based autonomous systems has been emerging as an important R&D topic in order to address increasing resiliency. In this session we will invite the industry experts to discuss the various aspects of this new field.

Monolithic 3-D (M3D) integration is a promising technology for achieving high performance and low-power consumption. However, the limitations of current M3D fabrication flows lead to performance degradation of devices in the top tier and unreliable interconnects between tiers. Fault localization at the tier level is therefore necessary to enhance yield learning, For example, tier-level localization can enable targeted diagnosis and process optimization efforts. In this article, we develop a graph neural network-based diagnosis framework to efficiently localize faults to a device tier. The proposed framework can be used to provide rapid feedback to the foundry and help enhance the quality of diagnosis reports generated by commercial tools. Results for four M3D benchmarks, with and without response compaction, show that the proposed solution achieves up to 32.86% improvement in diagnostic resolution with less than 1% loss of accuracy, compared to results from commercial tools. The proposed framework has also been demonstrated to be transferable to perform diagnosis on various design configurations without performance degradation.

Nanoscale interlayer vias (ILVs) in monolithic 3-D (M3D) ICs have enabled high-density vertical integration of logic and memory tiers. However, the sequential assembly of M3D tiers via wafer bonding is prone to variability in the immature fabrication process and manufacturing defects. The yield degradation due to ILV faults can be mitigated via dedicated test and diagnosis of ILVs using built-in self-test (BIST). Prior work has carried out fault localization for a regular 1-D placement of ILVs in the M3D layout where shorts are assumed to arise only between unidirectional ILVs. However, to minimize wirelength in M3D routing, ILVs may be irregularly placed by a place-and-route tool, and shorts can also occur between an up-going ILV and a down-going ILV. To test and localize faults in realistic ILV layouts, we present a new BIST framework that is optimized for test time and PPA overhead. We also present a graph-theoretic approach for representing potential fault sites in the ILVs and carry out inductive fault analysis to drop noncritical sites. We describe a procedure for optimally assigning ILVs to the BIST pins and determining the BIST configuration for test-cost minimization. Evaluation results for M3D benchmarks demonstrate the effectiveness of the proposed framework.

Monolithic 3D (M3D) integration is a promising technology for achieving high performance and low power consumption. However, the limitations of current M3D fabrication flows lead to performance degradation of devices in the top tier and unreliable interconnects between tiers. Fault localization at the tier level is therefore necessary to enhance yield learning, For example, tier-level localization can enable targeted diagnosis and process optimization efforts. In this paper, we develop a graph neural network-based diagnosis framework to efficiently localize faults to a device tier. The proposed framework can be used to provide rapid feedback to the foundry and help enhance the quality of diagnosis reports generated by commercial tools. Results for four M3D benchmarks, with and without response compaction, show that the proposed solution achieves up to 39.19% improvement in diagnostic resolution with less than 1% loss of accuracy, compared to results from commercial tools.

Monolithic 3D (M3D) integration is a promising technology for achieving high performance and low power consumption. However, the limitations of current M3D fabrication flows lead to performance degradation of devices in the top tier and unreliable interconnects between tiers. Fault localization at the tier level is therefore necessary to enhance yield learning, For example, tier-level localization can enable targeted diagnosis and process optimization efforts. In this paper, we develop a graph neural network-based diagnosis framework to efficiently localize faults to a device tier. The proposed framework can be used to provide rapid feedback to the foundry and help enhance the quality of diagnosis reports generated by commercial tools. Results for four M3D benchmarks, with and without response compaction, show that the proposed solution achieves up to 39.19% improvement in diagnostic resolution with less than 1% loss of accuracy, compared to results from commercial tools.

We propose TaintLock, a lightweight dynamic scan data authentication and encryption scheme that performs per-pattern authentication and encryption using taint and signature bits embedded within the test pattern. To prevent IP theft, we pair TaintLock with truly random logic locking (TRLL) to ensure resilience against both Oracle-guided and Oracle-free attacks, including scan deobfuscation attacks. TaintLock uses a substitution-permutation (SP) network to cryptographically authenticate each test pattern using embedded taint and signature bits. It further uses cryptographically generated keys to encrypt scan data for unauthenticated users dynamically. We show that it offers a low overhead, non-intrusive secure scan solution without impacting test coverage or test time while preventing IP theft.

The ubiquitous application of deep neural networks (DNN) has led to a rise in demand for AI accelerators. DNN-specific functional criticality analysis identifies faults that cause measurable and significant deviations from acceptable requirements such as the inferencing accuracy. This paper examines the problem of classifying structural faults in the processing elements (PEs) of systolic-array accelerators. We first present a two-tier machine-learning (ML) based method to assess the functional criticality of faults. While supervised learning techniques can be used to accurately estimate fault criticality, it requires a considerable amount of ground truth for model training. We therefore describe a neural-twin framework for analyzing fault criticality with a negligible amount of ground-truth data. We further describe a topological and probabilistic framework to estimate the expected number of PE's primary outputs (POs) flipping in the presence of defects and use the PO-flip count as a surrogate for determining fault criticality. We demonstrate that the combination of PO-flip count and neural twin-enabled sensitivity analysis of internal nets can be used as additional features in existing ML-based criticality classifiers.

We present a neural twin-based structural test pattern generation method for stuck-at faults in systolic array-based AI inferencing accelerators. The neural twin is a neural representation of the gate-level netlist of a processing element and it provides a one-to-one topological correspondence with the PE netlist. We leverage neural twin-enabled backpropagation for gradient computation to determine an input pattern that sensitizes a fault in the netlist. Our framework also supports pattern compaction for a batch of faults. Consequently, GPU-accelerated test-pattern generation is achieved with the proposed framework that can potentially detect hard-to-detect and random-pattern-resistant faults in AI accelerators. Experimental results for 4-bit, 8-bit, and 16-bit fixed-point accelerator arrays show the effectiveness of the proposed method.

Resistive random-access memory (RRAM) constitutes a promising technology for next-generation memory architectures due to its simple structure, high on/off ratio, and processing-in-memory ability. Its compatibility with emerging monolithic 3D (M3D) integration enables extremely high density using monolithic inter-tier vias (MIVs). However, both RRAM and M3D are susceptible to high defect rates due to immature manufacturing processes and process variations. Fault diagnosis for M3D-integrated RRAM and MIVs is therefore necessary to facilitate yield learning. In this work, we present a detailed characterization of RRAM faulty behaviors in the presence of process variations and manufacturing defects. We develop a diagnosis procedure by identifying appropriate reference resistance based on RRAM characteristics to efficiently distinguish fault origins. Results show that the proposed solution is compatible with existing test algorithms to significantly improve diagnostic resolution without affecting fault coverage.

The growing size of analog IPs has made targeted structural testing of such designs a challenging problem. We present a gradient-based automated test generation framework for analog circuits using neural twins, which are neural equivalents of the corresponding analog circuit. A neural twin is constructed by combining several FET-twins that lie in the paths between the circuit's inputs and observation points. Each FET-twin is a fully-connected neural network that models the IV characteristics of individual MOSFETs in the design. We train different variants of FET-twins that can predict both the output current and nodal voltage with more than 99% accuracy. We create an analog neural miter circuit, for which tests are generated using gradient ascent to maximize the loss between the faulty and fault-free versions of the neural twin. By computing gradients in a batchwise fashion for all the faults in the design, we develop a test compaction scheme that covers all faults with minimum number of test patterns. The neural twin-driven test generation method is interpretable, faster to simulate through GPUs, and guarantees convergence through backpropagation. We demonstrate the effectiveness of this framework by generating tests for structural defects in analog benchmark circuits. We show that our method outperforms an existing black-box optimization method that can be repurposed for test generation.

The ubiquitous application of deep neural networks (DNN) has led to a rise in demand for AI accelerators. DNN-specific functional criticality analysis identifies faults that cause measurable and significant deviations from acceptable requirements such as the inferencing accuracy. This paper examines the problem of classifying structural faults in the processing elements (PEs) of systolic-array accelerators. We first present a two-tier machine-learning (ML) based method to assess the functional criticality of faults. The problem of minimizing misclassification is addressed by utilizing generative adversarial networks (GANs). The two-tier ML/GAN-based criticality assessment method leads to less than 1% test escapes during functional criticality evaluation of structural faults. While supervised learning techniques can be used to accurately estimate fault criticality, it requires a considerable amount of ground truth for model training. We therefore describe a neural-twin framework for analyzing fault criticality with a negligible amount of ground-truth data. A recently proposed misclassification-driven training algorithm is used to sensitize and identify biases that are critical to the functioning of the accelerator for a given application workload. The proposed framework achieves up to 100% accuracy in fault-criticality classification in 16-bit and 32-bit PEs by using the criticality knowledge of only 2% of the total faults in a PE.

Monolithic 3D (M3D) integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method that requires only two test patterns to detect opens, stuck-at faults, and bridging faults (shorts) in ILVs. We also propose an extended BIST architecture for fault detection, called Dual-BIST, to guarantee zero ILV fault masking due to single BIST faults and negligible ILV fault masking due to multiple BIST faults. We analyze the impact of coupling between adjacent ILVs arranged in a 1D array in block-level partitioned designs. Based on this analysis, we present a novel test architecture called Shared-BIST with the added functionality of localizing single and multiple faults, including coupling-induced faults. We introduce a systematic clustering-based method for designing and integrating a delay bank with the Shared-BIST architecture for testing small-delay defects in ILVs with minimal yield loss. Simulation results for four two-tier M3D benchmark designs highlight the effectiveness of the proposed BIST framework.

Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes the limitations of the conventional through-silicon-via (TSV) and provides significant performance uplift and power reduction. However, the ultra-dense 3D interconnects impose significant challenges during physical design on how to best utilize them. Besides, the unique low-temperature fabrication process of M3D requires dedicated design-for-test mechanisms to verify the reliability of the chip. In this article, we provide an in-depth analysis on these design and test challenges in M3D. We also provide a comprehensive survey of the state-of-the-art solutions presented in the literature. This article encompasses all key steps on M3D physical design, including partitioning, placement, clock routing, and thermal analysis and optimization. In addition, we provide an in-depth analysis of various fault mechanisms, including M3D manufacturing defects, delay faults, and MIV (monolithic inter-tier via) faults. Our design-for-test solutions include test pattern generation for pre/post-bond testing, built-in-self-test, and test access architectures targeting M3D.

Accelerators for machine learning [artificial intelligence (AI)] inferencing applications are homogeneous designs composed of identical cores. Each core or processing element (PE) contains multiply-and-accumulate units, control logic, and registers for storing and forwarding weights and activations. Testing homogeneous array-based AI accelerator chips by running automatic test pattern generation (ATPG) at the array level results in a high CPU time and pattern count. We propose a constant-testable (C-testable) method for test generation at the PE level such that the ATPG effort does not increase with the number of PEs. Our results show that compared to the traditional array-level testing, the proposed method achieves up to$4.2\times $($3.5\times $),$1530\times $($2388\times $), and$170\times $($142\times $) reduction in the test pattern count, ATPG runtime, and test cycle count, respectively, for stuck-at (transition) faults in a$256\times 256$array, while preserving the test coverage. A reconfigurable scan architecture is introduced to enable the proposed C-testable solution for the entire accelerator array. The design-space exploration of a hierarchical test-compaction framework is presented. We also describe four debug solutions for fault localization and diagnosis.

The ubiquitous application of deep neural networks (DNNs) has led to a rise in demand for artificial intelligence (AI) accelerators. For example, the tensor processing unit from Google–based on a systolic array–and its variants are of considerable interest for DNN inferencing using AI accelerators. This article studies the problem of classifying structural faults in such an accelerator based on their functional criticality. We first analyze pin-level faults in the processing elements (PEs) of a systolic array. Simulation results for the LeNet network with 8-bit fixed-point, 16-bit floating-point (FP), and 32-bit FP data paths applied to the MNIST dataset show that over 93% of the pin-level structural faults in a PE are functionally benign. We present a greedy iterative framework for determining the criticality of stuck-at faults in a PE netlist and analyze the limitations of criticality analysis methods based on repeated fault simulations. We next present a scalable two-tier machine-learning (ML)-based method to assess the functional criticality of stuck-at faults in a computationally efficient manner. We address the problem of minimizing misclassification by utilizing generative adversarial networks (GANs). Two-tier ML/GAN-based criticality assessment leads to less than 1% test escapes during functional criticality evaluation of structural faults.

Monolithic 3D (M3D) integration has the potential to achieve significantly higher device density compared to TSV-based 3D stacking. Sequential integration of transistor layers enables high-density vertical interconnects, known as inter-layer vias (ILVs), However, high integration density and aggressive scaling of the inter-layer dielectric make M3D integrated circuits especially prone to process variations and manufacturing defects. We explore the impact of these fabrication imperfections on chip-performance and present the associated test challenges. We introduce two M3D-specific design-for-test solutions - a low-cost built-in self-test architecture for the defect-prone ILVs and a tier-level fault localization method for yield learning. We describe the impact of defects on the efficiency of delay fault testing and highlight solutions for test generation under constraints imposed by the 3D power distribution network.

Owing to the inherent fault tolerance of deep neural networks (DNNs), many structural faults in DNN accelerators tend to be functionally benign. In order to identify functionally critical faults, we analyze the functional impact of stuck-at faults in the processing elements of a 128×128 systolic-array accelerator that performs inferencing on the MNIST dataset. We present a 2-tier machine-learning framework that leverages graph convolutional networks (GCNs) for quick assessment of the functional criticality of structural faults. We describe a computationally efficient methodology for data sampling and feature engineering to train the GCN-based framework. The proposed framework achieves up to 90% classification accuracy with negligible misclassification of critical faults.

Carbon nanotube FETs (CNFETs) are emerging as an alternative to silicon devices for next-generation computing systems. However, imperfect carbon nanotube deposition during CNFET fabrication can lead to the formation of difficult-to-etch CNT aggregates in the active layer. These CNT aggregates can form parasitic CNFETs (para-FETs) that are modulated by adjoining gate contacts or back-end-of-line metal layers, thereby forming conditional shorts and stuck-at faults. We show that even weak (parametric) para-FETs can lead to a degraded static noise margin in CNFET-based design. We propose ParaMitE, a layout optimization method that horizontally flips selected standard cells in situ to minimize the number of para-FETs that can arise due to unetched CNTs. As we modify only the cell orientation (and not the cell placement), the impact on the power, timing, and wire length of the CNFET-based design is negligible. Simulation results for several benchmarks show that the proposed method can mitigate up to 60% of the possible para-FET locations (90% of the most critical locations) with only a 3% increase in the total wire length. ParaMitE can enable yield ramp-up at the foundry by providing guidance on which para-FETs can be avoided by design, and conversely, which CNT aggregates must be removed through processing steps.

Monolithic 3D(M3D) integration has the potential to achieve significantly higher device density compared to TSV-based 3D stacking. Sequential integration of transistor layers enables high-density vertical interconnects, known as inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make M3D integrated circuits especially prone to process variations and manufacturing defects. Furthermore, the sequential assembly of M3D tiers and immature fabrication process are prone to inter-tier coupling and performance variations. In view of the impact of these fabrication imperfections on chip performance and the associated test challenges, we describe two M3D-specific design-for-test solutions – a low-cost built-in self-test architecture for the defect-prone ILVs and a tier-level fault localization method for yield learning.

Owing to the inherent fault tolerance of deep neural network (DNN) models used for classification, many structural faults in the processing elements (PEs) of a systolic array-based AI accelerator are functionally benign. Brute-force fault simulation for determining fault criticality is computationally expensive due to many potential fault sites in the accelerator array and the dependence of criticality characterization of PEs on the functional input data. Supervised learning techniques can be used to accurately estimate fault criticality but it requires ground truth for model training. The ground-truth collection involves extensive and computationally expensive fault simulations. We present a framework for analyzing fault criticality with a negligible amount of ground-truth data. We incorporate the gate-level structural and functional information of the PEs in their "neural twins", referred to as "PE-Nets". The PE netlist is translated into a trainable PE-Net, where the standard-cell instances are substituted by their corresponding "Cell-Nets" and the wires translate to neural connections. Each Cell-Net is a pre-trained DNN that models the Boolean-logic behavior of the corresponding standard cell. In the PE-Net, every neural connection is associated with a bias that represents a perturbation in the signal propagated by that connection. We utilize a recently proposed misclassification-driven training algorithm to sensitize and identify biases that are critical to the functioning of the accelerator for a given application workload. The proposed framework achieves up to 100% accuracy in fault-criticality classification in 16-bit and 32-bit PEs by using the criticality knowledge of only 2% of the total faults in a PE.

Sensitivity to process variations and manufacturing defects are major showstoppers for the high-volume manufacturing of carbon nanotube field-effect transistors (CNFETs). These imperfections affect gate delay and may remain undetected when test patterns obtained using conventional test-generation techniques are used. We propose a new test generation method that takes CNFET-specific process variations into account and identifies multiple testable long paths through each node in a netlist. In contrast to state-of-the-art techniques, our method can also handle variations that have a nonlinear impact on the propagation delay. The generated test patterns ensure the detection of delay faults through the longest path, even under random CNFET process variations. The proposed method shows significant improvement in the statistical delay quality level (SDQL) compared with a state-of-the-art technique and a commercial ATPG tool for multiple benchmarks. We observed a minimum of 17.1% improvement in the SDQL offered by our patterns over a test set of the same size generated by the commercial tool. We also show that our method, when integrated with the conventional transition fault test flow, offers a significant improvement in the quality of test patterns under random variations. Moreover, the proposed method is flexible and can be easily extended to other emerging device technologies.

Monolithic 3D (M3D) ICs have emerged as a promising technology with significant improvement in power, performance, and area (PPA) over conventional 3D-stacked ICs. However, the sequential assembly of M3D tiers and immature fabrication process are prone to manufacturing defects and intertier process variations. Tier-level fault localization is therefore essential for yield ramp-up and diagnosis. Due to overhead concerns, only a limited number of observation points (OPs) can be inserted on the outgoing inter-layer vias (ILVs) of a tier to enable fault localization. We propose the computationally efficient NodeRank algorithm for observation-point insertion (OPI) on a small subset of outgoing ILVs. An ATPG-independent heuristic is presented, which is several orders-of-magnitude faster than ATPG fault simulation-based OPI. We introduce a metric called degree of fault localization to quantify the effectiveness of OPs. Evaluation results for two-tier M3D benchmark circuits show the effectiveness of the proposed method.

Accelerators for machine learning (AI) inferencing applications are homogeneous designs composed of identical cores. Each core, or processing element (PE), contains multiply-and-accumulate units, control logic, and registers for storing and forwarding weights and activations. Testing homogeneous array-based AI accelerator chips by running automatic test pattern generation (ATPG) at the array level results in a high CPU time and pattern count. We propose a constant-testable (C-testable) method for test generation at the PE level such that the ATPG effort does not increase with the number of PEs. Our results show that, compared to the traditional array-level testing, the proposed method achieves up to 4.2× (3.5 ×), 1530 × (2388 ×), and 170× (142×) reduction in the test pattern count, ATPG runtime, and test cycle count, respectively, for stuck-at (transition) faults in a 256 × 256 array, while preserving the test coverage. A reconfigurable scan architecture is introduced to enable C-testing for the entire accelerator array.

In this paper, we propose RTL-to-GDS design flow for monolithic 3D ICs (M3D) built with carbon nanotube field-effect transistors and resistive memory. Our tool flow is based on commercial 2D tools and smart ways to extend them to conduct M3D design and simulation. We provide a post-route optimization flow, which exploits the full potential of the underlying M3D process design kit (PDK) for power, performance and area (PPA) optimization. We also conduct IR-drop and thermal analysis on M3D designs to improve the reliability. To enhance the testability of our M3D designs, we develop design-for-test (DFT) methodologies and integrate a low-overhead built-in self-test module into our design for testing inter-layer vias (ILVs) as well as logic circuitries in the individual tiers. Our benchmark design is RISC-V Rocketcore, which is an open source processor. Our experiments show 8.1% of power, 19.6% of wirelength and 55.7% of area savings with M3D designs at iso-performance compared to its 2D counterpart. In addition, our IR-drop and thermal analyses indicate acceptable power and thermal integrity in our M3D design.

The ubiquitous application of deep neural networks (DNNs) has led to a rise in demand for artificial intelligence (AI) accelerators. This paper studies the problem of classifying structural faults in such an accelerator based on their functional criticality. We analyze the impact of stuck-at faults in the processing elements (PEs) of a $128 \times 128$ systolic array designed to perform classification on the MNIST dataset using both 32-bit and 16-bit data paths. We present a two-tier machine-learning (ML) based method to assess the functional criticality of these faults. We address the problem of minimizing misclassification by utilizing generative adversarial networks (GANs). The two-tier ML/GAN-based criticality assessment method leads to less than 1% test escapes during functional criticality evaluation.

Carbon-nanotube FETs (CNFETs) are potential successors to CMOS transistors; these emerging devices have a low intrinsic delay due to near-ballistic transport in carbon nanotubes (CNTs). As CNFETs are evaluated for circuit/system design, it is important to analyze variations in CNT process parameters. In this article, we present a systematic approach to quantify the impact of these imperfections on the transistor- and gate-level performances of CNT-based circuits. Process variations are investigated to identify the critical device parameters that have maximum impact on the device on-current. We also present a model that predicts the realistic CNFET yield in the presence of process variations. Finally, the impact of manufacturing defects, such as pinholes in the gate dielectric and parasitic CNFETs formed due to imperfect etching, are modeled and evaluated using HSPICE.

Monolithic 3D IC overcomes the limitation of the existing through-silicon-via (TSV) based 3D IC by providing denser vertical connections with nano-scale inter-layer vias (ILVs). In this paper, we demonstrate a thorough RTL-to-GDS design flow for monolithic 3D IC, which is based on commercial 2D place-and-route (P&R) tools and clever ways to extend them to handle 3D IC designs and simulations. We also provide a low-cost built-in-self-test (BIST) method to detect various faults that can occur on ILVs. Lastly, we present a resistive random access memory (ReRAM) compiler that generates memory modules that are to be integrated in monolithic 3D ICs.

Monolithic 3D integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method to detect opens, stuck-at faults (SAFs), and bridging faults (shorts) in ILVs. Two test patterns-all-1s and all-0s-are applied to the input side of a set of ILVs (e.g., making up a bus between two tiers). On the adjacent tier (the output side of the ILVs), the test responses are compacted to a 2-bit signature through space compaction. We prove that this compaction solution does not introduce any fault aliasing. Simulations results using HSPICE and M3D benchmark designs show that the proposed BIST method requires low area overhead and test time, but provides effective fault localization and the detectability of a wide range of resistive faults.

The emergence of non-volatile memories (NVM) such as resistive-oxide random access memory (RRAM), magnetoresistive random access memory (MRAM), and phase change memory (PCM) enables brain-inspired neuromorphic computing. However, due to immature fabrication process, NVMs are prone to process variations and manufacturing defects, which must be investigated for effective defect-to-fault mapping, high-coverage test generation, and diagnostics-driven yield learning. In this paper, we present a survey of research on fault modeling, test generation methodologies, and fault-tolerant design of neuromorphic computing systems based on RRAM and MRAM.

Resistive random-access memory (RRAM)-based computing systems (RCS) are being advocated for neural network acceleration. The memristor is the unit cell of an RCS and it is susceptible to process variations and manufacturing defects. Therefore, it is essential to tolerate faulty memristors to ensure intended system operation. We present the architecture of a novel processing element to tolerate both stuck-at and undefined-state faults in binary RRAM cells. We also describe a 4T1R reconfigurable cell-based crossbar design with an ancillary 3T mesh to provide 100% hardware fault tolerance for random and clustered fault distributions for up to 50% fault density. The proposed 4T1R cell is 2.04× smaller than the state-of-the-art neuromorphic SRAM cell. Evaluation results for binary pattern-matching and digit recognition applications demonstrate the effectiveness of our fault tolerance methodology.

Emerging devices are susceptible to process variations and manufacturing defects due to immature fabrication processes. Memristors constitute a promising emerging technology, but they are known to suffer from high defect rates that contribute to faulty behavior. It is therefore important to analyze memristor fault models and understand the root causes of defects and variations. We present a physics-based classification and analysis of memristor fault origins. These fault origins are systematically attributed to process variations and manufacturing defects. We also investigate coupling in dense memristor crossbars. This study of memristor fault origins and the resulting conclusions provides valuable feedback for the fabrication and the design of memristor-based circuits and systems.