In the post-layout simulation for large-scale integrated circuits, Transient Analysis (TA), determining the time-domain response over a specified time interval, is essential and time-consuming. Especially, a mass of backward steppings and low simulation efficiency occur without proper settings of Newton-Raphson (NR) initial solution and accurate Local Truncation Error (LTE) estimation. In this work, a novel multi-step irregular sequence prediction model (MISP-Net) is proposed to predict multiple NR initial solutions and precise LTE estimations by just one inference step. This model is constructed by an Irregular Multiple Timesteps Prediction Module (IMTP) and a Irregular Multi-step Solution Prediction Module (IMSP). In IMSP, to improve the irregular prediction performance, a Dual-branch Irregular Feature Pyramid (DIFP) equipped with lightweight Multi-Channel Irregular Time Attention (MITA) are designed. We assess the proposed MISP-Net in the real large-scale industrial circuits on a commercial SPICE simulator. Compared with the commercial SPICE and the SOTA ISPT-Net model, significant backward stepping reductions are achieved: up to 78.57% for NR nonconvergence case and 76.62% for LTE overlimit case, respectively. And the prediction time for NR initial solution in our model is remarkably reduced by up to 5.58× compared to the SOTA ISPT-Net model.

DC analysis holds critical importance in nonlinear circuit simulation, providing the essential precondition for transient and AC analyses. While Pseudo-Transient Analysis (PTA) and its variants excel in DC analysis, selecting the optimal PTA method for specific circuits remains challenging. To address this, we propose GE-LLM, a novel framework for optimal PTA method selection, which integrates Graph Neural Networks (GNNs) with Large Language Models (LLMs). The framework first converts circuit netlists into graph representations and employs a GNN-based graph encoder to capture essential circuit topologies. Subsequently, a novel text-graph alignment strategy bridges circuit topologies and textual descriptions, enabling the LLM to effectively comprehend multimodal information. Finally, we introduce a multi-perspective few-shot prompt that mitigates data scarcity by enabling effective in-context learning from limited circuit examples. Experimental results demonstrate that GE-LLM achieves a high selection accuracy of 0.9714 and improves the efficiency of DC analysis, yielding an average speedup of 2.89× in PTA steps (up to 12.14×) and 3.45× in Newton-Raphson iterations (up to 30.39×) compared to a commercial SPICE-like simulator.

IR drop analysis is crucial for ensuring the reliability and performance of integrated circuits (ICs) but poses computational challenges as the IC designs grow larger, especially for ultra deep-submicron VLSI designs. Deep learnings (DL) as the efficiency-promising solutions, mainly employ various CNN-based networks to achieve image-to-image IR drop predictions. However, they neglect and lose the power delivery network (PDN) global spatial features and cell instance topological information. This paper proposes a novel image-graph heterogeneous fusion framework (IGHF), which integrates the effectiveness and complementarity of dual branches (CNN and GNN) for higher prediction performance. In the CNN-based Power ScaleFusion Unet branch, the proposed long-range and local-detail encoder (LLE) integrates seamlessly with the hierarchical and adjacent compensation group (HACG) module. This design facilitates effective multi-scale global-to-local spatial power feature extraction within the PDN and enables adaptive high-to-low-level feature fusion and compensation in the decoder. Moreover, a cell voltage aware (CVA) module in the GNN branch is designed to adaptively aggregate PDN topological features of heterogeneous neighbors of different orders. Comparative experiments demonstrate that the proposed IGHF achieves significant accuracy improvements, outperforming the state-of-the-art MAUNet and widely-used IREDGe methods by considerable margins of 24.6% and 55.0% reduction in prediction error, while the prediction maps possess higher structural fidelity. Transfer experiments indicate that IGHF with transfer learning can improve the accuracy in real circuits with the few-shot real circuit test cases.

Sparse LU factorization is a vital technique in solving circuit linear equations, However, irregular data access patterns contribute to unsatisfactory computational efficiency and excessive memory usage. Conventional LU factorization methods generally involve two approaches: either they utilize space-intensive dense matrices for direct index-to-data mapping, or they inefficiently scour through indices to locate the positions of updated data elements. To resolve these challenges, we propose the Indexing-Efficient Sparse LU factorization (ISLU) in this work. A novel indexing-efficient member union is put forwarded to achieve efficient retrieval of indices within compressed formats, thereby significantly enhancing the LU decomposition efficiency. Furthermore, to expedite the establishment of indexing-efficient member union, we design, for the first time, parallel creating member union strategy for GPU platforms, which remarkably reduces the time overhead associated with constructing the proposed structures. Extensive experimental comparisons on 49 benchmark matrices and real SPICE transient simulations demonstrate that the performance enhancements by our proposed ISLU method are substantial, outperforming various excellent GPU and CPU solvers including commercial solvers.

Pseudo transient analysis (PTA) has been a promising solution for direct current (DC) analysis of transistor-level circuit simulation. Despite its popularity, PTA requires meticulous hyperparameter tuning for optimal performance. In this paper, we propose pseudo adjoint optimization, Soda-PTA, which models the PTA solution curve (which is used to measure convergence) using a neural ordinary differential equation (Neural ODE) and deriving explicit gradients of the Newton-Raphson (NR) iteration w.r.t. the PTA hyperparameters through the classic adjoint method, enabling effective optimization of the PTA hyperparameters. To generalize Soda-PTA for unseen circuits, we further introduce a graph convolution network to transfer optimal PTA hyperparameters from the other circuits to the target one. Soda-PTA is implemented in an out-of-the-box SPICE simulator. Through extensive experiments, Soda-PTA demonstrates superior acceleration performance: an average speedup of 1.53x over the state-of-the-art BoA-PTA while ensuring superior convergence and up to 22.12x speedup compared to the native PTA solver.