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Jan V. Zeman

dblp:189/0844 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1980
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 77% Reconfigurable computing and FPGAs · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital signal processing circuits
digital signal processor design
0.011980
A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic · IEEE Trans. Computers 1980
Reconfigurable computing and FPGAs › FPGA arithmetic
distributed arithmetic
0.011980
A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic · IEEE Trans. Computers 1980

Methods — techniques the papers use, named apart from their topics

microprogramming · 0.0distributed arithmetic · 0.0
YearPublicationVenuePosition
1980 A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic
abstract
This paper describes a general-purpose digital-signal processor which is constructed with 4 bit bipolar microprocessor slices. The signal processor is microprogrammable and contains special features which allow it to employ distributed arithmetic. Hence, the processor can achieve high sampling rates without using a hardware multiplier unit. The processor's architecture is presented and its micro-order structure is examined. The processor wordlength is 16 bit; its basic cycle time, 300 ns; its data memory size, 2K words; its control store size, 256 × 56 bits. It consumes 48 W of power and has special address processing hardware. Experimental results with a twelfth-order digital filter are demonstrated. The signal processor is also compared with several other signal processors of its class described in the literature.
Jan V. Zeman, H. Troy Nagle
IEEE Trans. Computers1