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Sergey Khvostov

dblp:189/1201 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
High-performance computing · 67% Energy-efficient computing · 33%
Interdisciplinary, comprehensive, and emerging computing
1 paper
Computational science and engineering · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing › performance optimization
many-core processor optimization
0.212016
Increasing molecular dynamics simulation rates with an 8-fold increase in electrical power efficiency · SC 2016
High-performance computing
performance optimization
0.212016
Increasing molecular dynamics simulation rates with an 8-fold increase in electrical power efficiency · SC 2016
Computational science and engineering › computational chemistry › molecular simulation
molecular dynamics
0.112016
Increasing molecular dynamics simulation rates with an 8-fold increase in electrical power efficiency · SC 2016

Methods — techniques the papers use, named apart from their topics

vectorization · 0.5software optimization · 0.5power measurement · 0.5
YearPublicationVenuePosition
2016 Increasing molecular dynamics simulation rates with an 8-fold increase in electrical power efficiency
abstract
Electrical power efficiency is a primary concern in designing modern HPC systems. Common strategies to improve CPU power efficiency rely on increased parallelism within a processor that is enabled both by an increase in the vector capabilities within the core and also the number of cores within a processor. Although many-core processors have been available for some time, achieving power-efficient performance has been challenging due to the offload model. Here, we evaluate performance of the molecular dynamics code LAMMPS on two new Intel®processors including the second generation many-core Intel®Xeon Phi™ processor that is available as a bootable CPU. We describe our approach to measure power consumption out-of-band and software optimizations necessary to achieve energy efficiency. We analyze benefits from Intel®Advanced Vector Extensions 512 instructions and demonstrate increased simulations rates with over 9X the CPU+DRAM power efficiency when compared to the unoptimized code on previous generation processors.
W. Michael Brown, Andrey Semin, Michael Hebenstreit, Sergey Khvostov, Steven J. Plimpton
SC4