Demo Data from EDBT 2026 / reviewers in the wild / expert
Zuo Lu
dblp:189/3693
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Storage systems · 80% Hardware reliability and fault tolerance · 20% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems
bit error rate |
0.4 | 1 | 2020 | Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Hardware reliability and fault tolerance › error correction
error-correcting codes |
0.4 | 1 | 2020 | Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Storage systems › flash and SSD
flash memory |
0.4 | 1 | 2020 | Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Storage systems › data representation › data encoding › error correction coding
LDPC codes |
0.4 | 1 | 2020 | Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Storage systems › flash and SSD › flash memory
NAND flash |
0.4 | 1 | 2020 | Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Methods — techniques the papers use, named apart from their topics
log-likelihood ratio optimization · 0.4error modes aware LDPC · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flashabstract3-D triple-level cell (3-D TLC) NAND flash has high storage density and capacity, but degrading data reliability due to high raw bit error rates induced by a certain number of program/erase cycles. To guarantee data reliability, low-density parity-check (LDPC) codes are selected as the error correction codes in modern flash memories because of strong error correction capability. However, directly adopting LDPC codes induces high decoding latency due to iterative updating of log-likelihood ratio (LLR) information in the decoding process. Increasing LLR information accuracy can greatly improve decoding performance. In this paper, we propose EMAL: using error modes aware LDPC codes for further enhancing the decoding performance of 3-D TLC NAND flash. We first obtain 3-D TLC error modes based on an FPGA testing platform, and then exploit the error modes to optimize LLR information and enable the decoding to converge at a high speed. The simulation results show that the decoding performance is significantly improved, resulting in reduced bit error rates and decoding latency. Fei Wu 0005, Meng Zhang 0014, Yajuan Du, Zuo Lu, Jiguang Wan 0001, Zhihu Tan, Changsheng Xie 0001 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 5 |
| 2018 | OSPADA: One-Shot Programming Aware Data Allocation Policy to Improve 3D NAND Flash Read PerformanceabstractCharge trap (CT) based 3D NAND flash is predominating the flash storage market due to higher density, better performance and endurance than planar flash. CT-based 3D flash programs multiple pages in a word line at a time, called one-shot programming, unlike planar flash which programs one page at a time. Solid state drives (SSDs) utilize the internal parallelism to improve the performance, but one-shot programming is likely to program logically sequential data into one parallel unit (i.e., a plane) and thus degrades the read parallelism. In this paper, we propose a one-shot programming aware data allocation policy, called OSPADA, to improve the read performance of CT flash based SSDs by enhancing read parallelism. OSPADA reorders written data to distribute logically sequential data into different parallel units using the distance aware round-robin strategy. Experimental results show that OSPADA improves the read performance by up to 22.8% compared with traditional dynamic data allocation policies. Fei Wu 0005, Zuo Lu, You Zhou 0009, Xubin He, Zhihu Tan, Changsheng Xie 0001 |
ICCD | 2 |
| 2016 | Extracting the vegetation phenology of India monsoon forestabstractThe India monsoon is changing under the global climate change, which influence the transformation from dry season to wet season, and then impact the photosynthetic activity and transpiration of tropical and subtropical monsoon forest. The descriptions of this kind of phenology in this area are still lacking, where various shapes of seasonal trajectories (e.g. “U” shape and “V” shape) and the special climate made the extraction of vegetation phenology difficult. However, current curve fitting approaches were inappropriate for simulating all these seasonal trajectories well. In this paper a modified logistic function method was proposed to extract the vegetation phenology (onset of greenness) of India monsoon forest. Due to the fine cloud detection method and the minimum NDVI composited technology, this modified approach had the ability to extract the vegetation phenology of India monsoon forest, which showed significant superiority over the compared six approaches in our previous study. The extracted time series of vegetation phenology by using this modified approach would facilitate the understandings of climate patterns and climate changes in the India monsoon area. Rong Shang, Ronggao Liu, Yang Liu 0120, Zuo Lu |
IGARSS | 4 |