Diego Martínez-Castro

dblp:189/4657 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2024
0000-0002-2618-0834ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Cryptographic primitives and cryptanalysis · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 77% Embedded and real-time systems · 23%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cryptographic primitives and cryptanalysis › random number generation
entropy source
0.812024
NDSTRNG: Non-Deterministic Sampling-Based True Random Number Generator on SoC FPGA Systems · IEEE Trans. Computers 2024
Cryptographic primitives and cryptanalysis
random number generation
0.812024
NDSTRNG: Non-Deterministic Sampling-Based True Random Number Generator on SoC FPGA Systems · IEEE Trans. Computers 2024
Reconfigurable computing and FPGAs
FPGA SoC
0.812024
NDSTRNG: Non-Deterministic Sampling-Based True Random Number Generator on SoC FPGA Systems · IEEE Trans. Computers 2024

Methods — techniques the papers use, named apart from their topics

non-deterministic sampling · 1.5linear feedback shift register · 1.5
YearPublicationVenuePosition
2024 NDSTRNG: Non-Deterministic Sampling-Based True Random Number Generator on SoC FPGA Systems
abstract
Random number generation is essential for applications in simulation, numerical analysis, and data encryption. The ubiquitous presence of system-on-chip (SoC) field-programmable gate array (FPGA) embedded devices in critical sectors necessitates robust random number generators (RNGs) that operate within these specialized environments. Traditional RNGs in GNU/Linux systems derive entropy from peripheral hardware events, which are scarce in SoC FPGA platforms lacking standard PC peripherals. Addressing this challenge, this paper proposes a novel random number generator named NDSTRNG that leverages the unique hardware structure of the SoC FPGA and the inherent randomness of GNU/Linux. The proposed generator employs a non-deterministic sampling model to circumvent reliance on various peripherals while ensuring unbiased output via a linear feedback shift register (LFSR)-based post-processing method. We implement this random number generator in SoC FPGA GNU/Linux using minimal FPGA resources and only one Linux task for sampling. NDSTRNG achieved a throughput exceeding 700 Kbps. Moreover, the entropy source of the generator is evaluated using NIST SP 800-90B, while the quality of the generated random numbers is assessed through ENT, NIST SP 800-22, and DIEHARDER. The results confirm that NDSTRNG meets the stringent criteria for both high-quality and high-speed random number generation, making it suitable for deployment in communication, defense, and medical domains where reliable RNGs are indispensable.
Yucong Chen, Yanshan Tian, Rui Zhou 0005, Diego Martínez-Castro, Deke Guo, Qingguo Zhou
IEEE Trans. Computers4
2016 Distributed multi-agent architecture for real-time wireless control networks of multiple plants
Apolinar González, Walter A. Mata-López, Vrani Ibarra-Junquera, Alberto Ochoa 0001, Diego Martínez-Castro, Alfons Crespo
Eng. Appl. Artif. Intell.5