Aiying Guo

dblp:189/8754 · DBLP profile ↗
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6ranked-venue papers
2as first author
6since 2021 · last 2026
0000-0002-0817-6161ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021Graphics, computer vision, multimedia, augmented reality and games · 2 · 1 first-author · 2 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021
YearPublicationVenuePosition
2026 PESSANet: prior-enhanced selectable sparse attention network for image super-resolution
Haocan Jiang, Aiying Guo
Multim. Syst.3
2025 Single-image super-resolution via lightweight shuffle feature fusion network
Aiying Guo, Zijun Deng
Multim. Syst.1
2025 CA-DDP: congestion-aware dynamic dimension prioritization for power-efficient routing algorithm in 3D Network-on-Chip
Feng Ran, Aiying Guo, Xuecheng Sun
J. Supercomput.4
2024 An Efficient Sparse Blocks Inference Method for Image Editing Based on Diffusion Models
abstract
Image editing methods based on diffusion models are significantly superior to traditional methods. However, due to their slow sampling speed, high computational complexity, and weak data generalization ability, these have encountered certain limitations in practical applications. This paper proposes an efficient sparse blocks inference method for diffusion models to address this issue. It also compensates and trains the sampled feature maps by reusing low-frequency information and introduces Lp-norm to replace Euclidean distance to calculate the loss function, thereby enhancing the reconstruction effect of high-frequency image features. This method takes low-frequency sparse block data inputs as constraints, using the masks of the difference and converting them into indices to achieve the reproduction of high-resolution data. Experiments on the LSUN and CelebAHQ dataset, our method improves the inference speed of DDIM by 2.68 ×, PD by 1.53 × and SDEdit by 5.5 ×, reduces the computational complexity of DDIM by 4.1 ×, PD by 1.7 × and SDEdit by 4.8 ×.
Zhuochao Yang, Aiying Guo
IJCNN3
2024 A Constant-Quiescent-Current and Fast-Transient CL-LDO with 99.99% Efficiency Using Dynamic Embedded Slew-Rate Enhancement Circuit
abstract
This paper presents a low constant quiescent current and fast transient response capacitor-less low dropout regulator (CL-LDO) with high current efficiency, achieved using a dynamic slew-rate enhancement (SRE) circuit. The proposed CL-LDO achieves a fast transient response without requiring additional current under heavy loads, enabling a peak current efficiency of 99.99%. Designed using a 55-nm standard CMOS process, the CL-LDO consumes a quiescent current of 10 µA. It can deliver 0.2-100 mA of load current at a 1.0-V output from a 1.2-V to 1.5-V supply voltage. Additionally, it achieves a settling time of 0.418 µs and an overshoot/undershoot voltage of 74 mV/166 mV for load steps ranging from 0.2 mA to 100 mA, with an edge time of 0.1 µs.
Aiying Guo
ISCAS2
2024 An energy-efficient image filtering interpolation algorithm using domain-specific dynamic reconfigurable array processor
Aiying Guo, Enlin Lin
Integr.1