The unpredictable inherent error behavior of approximate computing introduces both new security threats and opportunities to design novel security primitives/strategies. This work proposes a methodology that exploits stochastic timing errors of a pipelined datapath caused by voltage scaling to design an optimized processor-based physical unclonable function (PUF) for approximate computing. To verify the effectiveness of this method, a pipelined arithmetic architecture is implemented at a 45 nm technology node, and voltage scaling is applied to extract PUF bits. With reduced supply voltage, harvested PUF bits show increased uniqueness. Moreover, proposed divergent delay path selection based on intermediary error behavior exhibits improved PUF uniqueness vs an unmodified datapath. A design optimization methodology is applied introducing new PUF metrics - gain (G) and performance power ratio (PPR). Using these metrics, the optimum scaled voltage range is identified for enhanced PUF performance. The optimized PUF shows maximum uniqueness of 49%, and reliability of 92% with a temperature range of -20${\circ }$C to 70${\circ }$C. Further, the proposed PUF with approximate computing achieves markedly improved G and PPR relative to the exact case. With better uniqueness, reliability, and low resource utilization, the proposed PUF methodology is highly suitable for securing approximate computing applications.

The rapid growth of AI workloads is driving interest in Approximate Computing (AxC) as a means to enable low-cost, energy-efficient inference in resource-constrained systems. By introducing controlled inaccuracies, AxC can deliver substantial gains in power, performance, and area (PPA) while leveraging the inherent error tolerance of many AI models. Achieving this potential requires adapting existing frameworks to support the design and optimization of neural networks with approximate operators. Modern AxC research extends beyond accuracy-PPA trade-offs to address reliability and security, reducing redundancy overheads and exploring the distinctive side-channel implications of approximation. Application-aware approaches, such as those for spiking neural networks, show that tailoring approximation to workload-specific error behavior can surpass generic strategies. This article examines AI-guided design methods and the interplay between efficiency, reliability, and security, highlighting how these interconnected facets can advance embedded and high-performance computing.

Emerging low-energy computing technologies, in particular approximate computing, are becoming increasingly relevant in key applications. A significant use case for these technologies is reduced energy consumption in Artificial Neural Networks (ANNs), an increasingly pressing concern with the rapid growth of AI deployments. It is essential we understand the security implications of approximate computing in an ANN context before this practice becomes commonplace. In this work, we examine the test case of approximate ANN processing elements (PE) in terms of information leakage via the power side channel. We perform a weight extraction correlation Power Analysis (CPA) attack under three approximation scenarios: overclocking, voltage scaling, and circuit level bitwise approximation. We demonstrate that as the degree of approximation increases the Signal to Noise Ratio (SNR) of power traces rapidly degrades. We show that the Measurement to Disclosure (MTD) increases for all approximate techniques. An MTD of 48 under precise computing is increased to at minimum 200 (bitwise approximate circuit at $\mathbf{2 5 \%}$ approximation), and under some approximation scenarios $\gt1024$. i.e. an increase in attack difficulty of at least x4 and potentially over x20. A relative Security-Power-Delay (SPD) analysis reveals that, in addition to the across the board improvement vs precise computing, voltage and clock scaling both significantly outperform approximate circuits with voltage scaling as the highest performing technique.

Recent hardware developments in artificial intelligence (AI) edge devices expect architectures to support multiply and accumulation operations while preserving high inference accuracy and energy efficiency. This work proposes a compute in-memory (CiM) cell design with steep slope Negative capacitance field effect transistors (NCFET) for energy efficient computing architectures. The NCFET based 8T SRAM cell has been designed and analyzed for performance metrics such as noise margins and energy consumption during read/write modes for an optimum Ferroelectric layer thickness (Tfe) at VDD=0.3 V and 0.5V. Further, the NCFET 8T SRAM cell has been modified to realize energy efficient operations such as NCFET CiM based 2-input AND gate, NCFET CiM based 2-input XOR gate and NCFET CiM based half adder. Proposed NCFET CiM AND logic design exhibit ~5.85x lower energy consumption, NCFET CiM XOR logic design has ~3.29x lower energy consumption and NCFET CiM half adder logic design has ~6.57x lower energy consumption in comparison to equivalent baseline 40nm CMOS designs at VDD=0.5V.

Approximate computing has great potential in the design of high-performance and energy-efficient systems. The inherent stochastic error behavior of approximate computing introduces both new security threats and opportunities to enhance security. This work proposes a novel methodology that exploits stochastic timing errors of a pipelined datapath to design a processor based physically unclonable function (PUF) for approximate computing. This methodology uses divergent delay path selection based on intermediary error behaviour to improve the PUF uniqueness vs. an unmodified datapath, even when only moderate voltage scaling is applied. To verify the effectiveness of this method, a pipelined fast fourier transform (FFT) butterfly architecture is implemented at 45nm technology node, and a voltage over scaling technique is applied to extract PUF bits. The proposed methodology achieves a maximum uniqueness of 48.5% whereas conventional design uniqueness is limited to 43%. Overall, the proposed design shows a maximum of ~7% higher uniqueness and ~10% higher reliability (for iso uniqueness) compared to the conventional pipelined design.

This paper exploits tunnel field-effect transistors (TFET) unique asymmetrical device characteristics, demonstrating discriminant circuits for pattern recognition useful in machine learning-based VLSI and IoT designs. In contrast to unidirectional current conduction in TFET, it exhibits significant p-i-n leakage current with increase in negative drain-to-source voltage. Due to this characteristics, TFET transmission gate exhibits distinct behavior. Exploiting this behavior, a ring oscillator (RO) is designed that can sense the changes in operating frequency with response to the pattern of control bits. Utilizing this RO, a discriminant circuit is demonstrated which is highly energy efficient with an ultra-low energy consumption of 34.5 pJ at supply voltage of 0.4 V and much suits the demands of emerging machine learning-based VLSI systems. The simplicity of discriminant circuit makes the architecture of pattern recognition engine simpler and reduces the energy overheads.

Tunneling Field-Effect Transistor (TFET) is a leading future transistor option for next generation VLSI applications and Internet of things (IoT). Many have demonstrated the energy efficiency of TFET circuits. In this work, we demonstrate for the first time utilizing TFET ambipolar device characteristics for jitter generation in post-processing circuits of true random number generators (TRNGs) and suitability for enhancing hardware security of IoT platforms. Device and circuit design challenges for TFET based transceiver designs for capacitive coupled interconnect in 3DIC and on-chip low dropout digital voltage regulators (DLDOs) are further explored towards energy efficient IoT platforms.