Under the threat of quantum computers, the public-key cryptosystems need to transition to the Post-Quantum Cryptography (PQC) standards. However, this migration process is hindered by the diverse mathematical structures of PQC standards as well as the side-channel attacks, especially for the resource-constrained and physically accessible edge devices. To address this issue, we present ARV-Q, an adaptive RISC-V vector processor that efficiently offers unified support of PQC standards and side-channel security enhancement. Firstly, we propose an adaptive RISC-V-based computing paradigm to adapt to PQC algorithms across diverse mathematical bases, the core of which is a crypto extension supporting all PQC standards plus schemes in the fourth round in NIST standardization process. This crypto extension can well cooperate with the RISC-V Vector Extension (RVV) and is capable of adaptive operator-type support. Second, we design a highly resource-efficient vector crypto engine featuring versatile Butterfly Units and multi-Selected-Element-Width-adaptive modular arithmetic constructs, achieving high hardware utilization with configurable parameter settings. The crypto engine is integrated into the RISC-V core via an agile extension interface capable of bridging all types of register transfers. Besides, due to the capability of cooperative hybrid vector computing of RVV and crypto extension, ARV-Q can flexibly adapt to side-channel attacks with no hardware overhead while maintaining high performance. ARV-Q is implemented in 22nm process, and post-layout simulations are conducted. Results outperform the state-of-the-art counterparts in primary PQC standards with 1.21-5.14× better latency and more than 4.41× better area efficiency.

This article consists only of a collection of slides from the author's conference presentation.

The open source RISC-V ISA has been quickly gaining momentum. This paper presents Xuantie-910, an industry leading 64-bit high performance embedded RISC-V processor from Alibaba T-Head division. It is fully based on the RV64GCV instruction set and it features custom extensions to arithmetic operation, bit manipulation, load and store, TLB and cache operations. It also implements the 0.7.1 stable release of RISCV vector extension specification for high efficiency vector processing. Xuantie-910 supports multi-core multi-cluster SMP with cache coherence. Each cluster contains 1 to 4 core(s) capable of booting the Linux operating system. Each single core utilizes the state-of-the-art 12-stage deep pipeline, out-of-order, multi-issue superscalar architecture, achieving a maximum clock frequency of 2.5 GHz in the typical process, voltage and temperature condition in a TSMC 12nm FinFET process technology. Each single core with the vector execution unit costs an area of 0.8 mm2, (excluding the L2 cache). The toolchain is enhanced significantly to support the vector extension and custom extensions. Through hardware and toolchain co-optimization, to date Xuantie-910 delivers the highest performance (in terms of IPC, speed, and power efficiency) for a number of industrial control flow and data computing benchmarks, when compared with its predecessors in the RISC-V family. Xuantie-910 FPGA implementation has been deployed in the data centers of Alibaba Cloud, for applicationspecific acceleration (e.g., blockchain transaction). The ASIC deployment at low-cost SoC applications, such as IoT endpoints and edge computing, is planned to facilitate Alibaba’s end-to-end and cloud-to-edge computing infrastructure.