Demo Data from EDBT 2026 / reviewers in the wild / expert
Yu-Chuan Pi
dblp:19/10064
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2012
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 96% Distributed systems · 4% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › layout verification
design rule checking |
0.3 | 2 | 2012 | A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 A distributed algorithm for layout geometry operations · DAC 2011 |
Electronic design automation › physical design
layout verification |
0.3 | 2 | 2012 | A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 A distributed algorithm for layout geometry operations · DAC 2011 |
Electronic design automation › physical design
mask optimization |
0.3 | 2 | 2012 | A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 A distributed algorithm for layout geometry operations · DAC 2011 |
Electronic design automation
physical design |
0.3 | 2 | 2012 | A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 A distributed algorithm for layout geometry operations · DAC 2011 |
Distributed systems
distributed algorithms |
0.0 | 1 | 2012 | A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Methods — techniques the papers use, named apart from their topics
distributed layout partitioning · 0.1distributed algorithm · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2012 | A Hierarchy-Based Distributed Algorithm for Layout Geometry OperationsabstractThis paper introduces a novel distributed algorithm for performing the layout geometry operations usually found in design rule checking, layout verification, and mask synthesis. A large number of machines are typically available to the user during the mask synthesis flow. As multiple machines or cores become more ubiquitous, even designers using layout verification tools will have access to a large set of machines. Therefore, an efficient and scalable distributed algorithm for performing sequences of layout geometry operations will be of great value to both designers and mask synthesis engineers. Given a layout and a sequence of layout geometry operations, the proposed algorithm divides the layout into several partitions. The given sequence of layout geometry operations is executed in parallel on different partitions. New partitions are derived from the original set of partitions and the sequence of geometry operations is repeated on larger partitions with much fewer polygons. This process continues until it produces a partition that covers the entire layout area. A key feature of the proposed algorithm is that it is correct-by-construction, i.e., each partition is guaranteed to generate a subset of the correct results. Complete and correct results are generated for each layout geometry operation for the entire layout when the operation completes execution on all the partitions. The proposed algorithm was implemented in Gearman, an open-source distributed framework. Results on large industrial layouts show good performance and scalability. Kai-Ti Hsu, Subarna Sinha, Yu-Chuan Pi, Tsung-Yi Ho |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 2011 | A distributed algorithm for layout geometry operationsabstractThis paper introduces a novel distributed algorithm for performing layout geometry operations usually found in design rule checking, layout verification and/or mask synthesis. Typically, during the mask synthesis flow, a large number of machines are available to the user. Also, as multiple machines/cores become more ubiquitous, even designers using layout verification tools will have access to a large set of machines. Having an efficient and scalable distributed algorithm for performing sequences of layout geometry operations will be of great value to both the designer and the mask synthesis engineer. Kai-Ti Hsu, Subarna Sinha, Yu-Chuan Pi, Charles C. Chiang, Tsung-Yi Ho |
DAC | 3 |