In recent years, the complexity of neural network (NN) models has increase continuously, resulting in a substantial increase in multiply-accumulate (MAC) operations. Therefore, the need for area- and power-efficient DRAM compute-in-memory (CIM) designs has become a pressing issue. The proposed CIM design uses the reverse rotating charge sharing (RRCS) technique to save 79% of silicon area compared to conventional designs. In addition, the use of the proposed low-threshold prediction technique can reduce analog-to-digital converter (ADC) calculations by 25% and ADC power consumption by 17%. Energy efficiency and area reduction are 10x and 1900x, respectively, higher than previous CIM designs.

The conventional capacitor-switch-inductor (C-S-L) topology suffers from significant conduction loss and sluggish transient response due to the series power switches conduction inherent in its structure. To address these limitations, the proposed rotated hybrid converter adopts a rotated mechanism and parallel conduction within the capacitor-two-switch-inductor (C-2S-L) topology, effectively reducing current stress on components. This approach enhances efficiency while mitigating the effects of parasitic inductance from bond wires. During transient conditions, all C-2S-L stages can be simultaneously activated, enabling a near-full duty cycle (D). Experimental results demonstrate a minimal undershoot of 96 mV and a fast settling time of 0.92 μs during a load step from 2 A to 10 A within 20 ns. Additionally, the converter integrates phase shedding, dynamically adjusting the number of active phases according to load conditions to optimize efficiency across a broad load range. Therefore, the proposed C-2S-L topology achieves a peak efficiency of 92.6% at an output voltage (VOUT) of 1.2 V and a load current (ILOAD) of 3A.

This paper proposes a flying-capacitor sharing dynamic four-path (FCSD-4P) hybrid converter, designed to achieve a duty cycle (D) ranging from 0% to 100%, addressing the conventional limitation of D2. In a 6V to 1.8V conversion, the converter achieves a peak efficiency of 94.2%.

In this paper, the proposed multi-phase (MP) bidirectional dual Gallium-Nitride (GaN) controlled rectifier (GCR) uses dual GCR with the pre-charge technique to reduce third quadrant operation by minimizing dead time to 0.12ns and 0.13ns, and lowering the negative VDS to −0.6V and −0.8V in buck and boost operation, respectively. This work is the first research for monolithic bidirectional energy transfer with a two-switch-only topology. With the help of MP-accelerated current control and the GCR dynamic ramp generator, the voltage variation on the high-voltage (HV) side and low-voltage (LV) side can be reduced to less than 50mV and to 40mV, respectively, during buck and boost operation transitions. Moreover, the recovery time is effectively reduced and current balance between the four phases can be achieved within 7 cycles (=350ns). The peak efficiency is as high as 95.5% and 94.2% in buck and boost operation, respectively.

This paper proposes a two-phase hybrid buck-boost converter, which meets the criteria of USB PD 3.1, with an auxiliary inductor LAUX to achieve soft switching by the zero voltage switching (ZVS) technique at light loads. Besides, two interleaving phases can reduce the inductor current to half of that conventional design. Benefiting from a coupled inductor with a negative mutual inductance (M$_{\mathrm {L(AC)}}$becomes small to achieve low output voltage ripple due to large equivalent inductance Leq in a steady state. Based on the loading current, the phase shedding can change the number of driving phases for high efficiency. Moreover, a transient enhancement circuit is proposed to speed up transient response time. The proposed circuit achieves the maximum inductor current ripple reduction of 9.09% and the maximum P$_{\mathrm {AC\_loss}}$reduction of 17.36% at D=0.5. Experimental results show 96.1% peak efficiency. In the case of the load step 0.5A to 5A, the recovery time and undershoot are reduced to$10.7\mu $s and 133mV, respectively, and in the case of the load step 5A to 0.5A, the recovery time and overshoot are reduced to$9.4\mu $s and 147mV, respectively.