Demo Data from EDBT 2026 / reviewers in the wild / expert
Hiroshi Takatori
dblp:19/10713
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2000
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
2 papers |
Physical-layer communications · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Physical-layer communications
digital subscriber line |
0.0 | 2 | 2000 | Theoretical and practical limits of next-generation high-speed digital subscriber loops · IEEE Trans. Commun. 2000 Line Equalizer for a Digital Subscriber Loop Employing Switched Capacitor Technology · IEEE Trans. Commun. 1982 |
Physical-layer communications › modulation › waveform design
power spectral density optimization |
0.0 | 1 | 2000 | Theoretical and practical limits of next-generation high-speed digital subscriber loops · IEEE Trans. Commun. 2000 |
Physical-layer communications › interference
crosstalk |
0.0 | 1 | 2000 | Theoretical and practical limits of next-generation high-speed digital subscriber loops · IEEE Trans. Commun. 2000 |
Physical-layer communications › interference › crosstalk
near-end crosstalk |
0.0 | 1 | 2000 | Theoretical and practical limits of next-generation high-speed digital subscriber loops · IEEE Trans. Commun. 2000 |
Integrated circuit design
analog and mixed-signal circuits |
0.0 | 1 | 1982 | Line Equalizer for a Digital Subscriber Loop Employing Switched Capacitor Technology · IEEE Trans. Commun. 1982 |
Integrated circuit design › analog and mixed-signal circuits › mixed-signal circuit design
switched-capacitor circuits |
0.0 | 1 | 1982 | Line Equalizer for a Digital Subscriber Loop Employing Switched Capacitor Technology · IEEE Trans. Commun. 1982 |
Methods — techniques the papers use, named apart from their topics
preemphasis/deemphasis · 0.0simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2000 | Theoretical and practical limits of next-generation high-speed digital subscriber loopsabstractFor the single-pair HDSL (HDSL2), the concept of having different upstream and downstream power spectral densities is highlighted. The signal-to-noise ratio (SNR) at the input of the central office HDSL terminal unit (HTU-C) can be enhanced by boosting the power output of the remote user HDSL terminal unit (HTU-R). Further improvement in performance can be achieved by reducing the HTU-C NEXT interference. Two techniques are proposed to reach this goal. The first approach is to reduce the HTU-C transmitter power in the downstream direction for shorter reach cables. The second approach is borrowed from the analog frequency-modulation preemphasis/deemphasis frequency tilting in the upstream direction. Combining the three techniques leads to at least 6-dB SNR margin improvement for the full reach carrier serving area loops. Ahmed F. Shalash, Hiroshi Takatori |
IEEE Trans. Commun. | 2 |
| 1982 | Line Equalizer for a Digital Subscriber Loop Employing Switched Capacitor TechnologyabstractA new line equalizer system for time compression burstmode digital suhscriber loop transmission that can equalize a line with multiple bridged taps (BT's) is developed. Using the developed equalizer, up to 5 km (0.4 mmφ) line length and four BT connections can be equalized at a data rate of 80 kbits/s in each direction. The equalizer is composed of a variable gain\surd{f}step equilizer, a decision feedback automatic equalizer, and a newly developed wave difference method (WDM) timing extraction PLL. In order to fabricate the whole circuit on a single-chip LSI, most of the analog portion is organized using; switched capacitor technology. In this paper, the system design concept, circuit configuration, and results of simulations and experiiments are described. Toshiro Suzuki, Hiroshi Takatori, Makoto Ogawa, Keiji Tomooka |
IEEE Trans. Commun. | 2 |