Demo Data from EDBT 2026 / reviewers in the wild / expert
Thomas S. Payne
dblp:19/10972
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1982
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
circuit partitioning |
0.0 | 1 | 1982 | Automated partitioning of hierarchically specified digital systems · DAC 1982 |
Electronic design automation › design methodology
hierarchical design |
0.0 | 1 | 1982 | Automated partitioning of hierarchically specified digital systems · DAC 1982 |
Electronic design automation
physical design |
0.0 | 1 | 1982 | Automated partitioning of hierarchically specified digital systems · DAC 1982 |
Methods — techniques the papers use, named apart from their topics
iterative improvement · 0.0heuristic partitioning · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1982 | Automated partitioning of hierarchically specified digital systemsabstractThis paper describes a heuristic algorithm for automatically partitioning digital systems. High- level information contained within a hierarchical design is used to increase the effectiveness of this algorithm. This algorithm uses a constructive process to build a physical design of a hierarchically specified logic design. An iterative improvement step is then done. Thomas S. Payne, William M. van Cleemput |
DAC | 1 |