Demo Data from EDBT 2026 / reviewers in the wild / expert
Junichiro Tsuchiya
dblp:19/1366
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Interconnection networks and networks-on-chip · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip
low-latency communication |
0.1 | 1 | 2007 | Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs · IEEE Trans. Parallel Distributed Syst. 2007 |
Interconnection networks and networks-on-chip › network interface
network interface card |
0.1 | 1 | 2007 | Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs · IEEE Trans. Parallel Distributed Syst. 2007 |
Interconnection networks and networks-on-chip
remote direct memory access |
0.1 | 1 | 2007 | Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs · IEEE Trans. Parallel Distributed Syst. 2007 |
Interconnection networks and networks-on-chip
cluster interconnect |
0.0 | 1 | 2007 | Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs · IEEE Trans. Parallel Distributed Syst. 2007 |
Methods — techniques the papers use, named apart from their topics
hardwired logic · 0.1PIO-based communication · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2007 | Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCsabstractIn this paper, “Martini,” a network interface controller chip for our original network called RHiNET is described. Martini is designed to provide high-bandwidth and low-latency communication with small overhead. To obtain high performance communication, protected user-level zero-copy RDMA communication functions are completely implemented by a hardwired logic. Also, to reduce the communication latency efficiently, we have proposed PIO-based communication mechanisms called “On-the-fly (OTF)” and have implemented them on Martini. The evaluation results show that Martini connected to a 64bit/66MHz PCI-bus achieves 470MByte/s maximum bidirectional bandwidth and 1.74 μsec minimum latency on host-to-host memory copying. Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano |
IEEE Trans. Parallel Distributed Syst. | 3 |
| 2003 | Performance Evaluation of RHiNET-2/NI: A Network Interface for Distributed Parallel Computing SystemsabstractRHiNET-2/NI is a network interface for a parallel and distributed computing system with network connected PCs. The core of the network interface is an ASIC network controller chip Martini, which provides low-latency and large-bandwidth communication. Evaluation results show that it achieves almost full bandwidth of the 66MHz/64bit PCI bus, which is much larger than that of Myrinet-2000. The performance of a small prototype parallel system achieves almost linear speed up. Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hideharu Amano, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh |
CCGRID | 3 |
| 2002 | RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing
Naoyuki Izu, Tomonori Yokoyama, Junichiro Tsuchiya, Konosuke Watanabe, Hideharu Amano |
FPL | 3 |