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Feng-Yi Chiang

dblp:19/1813 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 61% Reconfigurable computing and FPGAs · 30% Energy-efficient computing · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA power reduction		 0.011998
A Re-engineering Approach to Low Power FPGA Design Using SPFD · DAC 1998
Electronic design automation
logic synthesis		 0.011998
A Re-engineering Approach to Low Power FPGA Design Using SPFD · DAC 1998
Electronic design automation › logic synthesis › technology mapping
technology remapping		 0.011998
A Re-engineering Approach to Low Power FPGA Design Using SPFD · DAC 1998
Energy-efficient computing › low-power design
power optimization		 0.011998
A Re-engineering Approach to Low Power FPGA Design Using SPFD · DAC 1998

Methods — techniques the papers use, named apart from their topics

SPFD-based resynthesis · 0.0
YearPublicationVenuePosition
1998 A Re-engineering Approach to Low Power FPGA Design Using SPFD
abstract
In this paper, we present a method to re-synthesize Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) for low power design after technology mapping, placement and routing are performed. We use Set of Pairs of Functions to be Distinguished (SPFD) to express functional permissibility of each signal. Using different propagations of SPFD to fan-in signals, we change the functionality of a PLB (Programmable Logic Block) which drives large loading into one with low transition density. Experimental results show that our method can reduce on average 12% power consumption compared to the original circuits without affecting placement and routing.
Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang
 DAC2