This work presents a 16MHz on_chip oscillator based on a frequency_locked loop (FLL) which is radiation hardened by design and intended for space applications. The oscillator maintains a high temperature stability over a wide range oftemperatures, process and voltage variations. The FLL presents a 7-stage current starved ring oscillator using output signal combiners for lower radiation sensitivity. Furthermore, the system presents high reconfigurability by using several DACs to adjust the oscillator’s output frequency and the temperature slope dependency. This reconfigurability is especially useful to maintain all performances across PVT variations.

This paper presents fuzzy c-means-based yield estimation (FUZYE), a methodology that reduces the time impact caused by Monte Carlo (MC) simulations in the context of analog integrated circuits (ICs) yield estimation, enabling it for yield optimization with population-based algorithms, e.g., the genetic algorithm (GA). MC analysis is the most general and reliable technique for yield estimation, yet the considerable amount of time it requires has discouraged its adoption in population-based optimization tools. The proposed methodology reduces the total number of MC simulations that are required, since, at each GA generation, the population is clustered using a fuzzy c-means (FCMs) technique, and, only the representative individual (RI) from each cluster is subject to MC simulations. This paper shows that the yield for the rest of the population can be estimated based on the membership degree of FCM and RIs yield values alone. This new method was applied on two real circuit-sizing optimization problems and the obtained results were compared to the exhaustive approach, where all individuals of the population are subject to MC analysis. The FCM approach presents a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. Moreover, a k-means-based clustering algorithm was also tested and compared with the proposed FUZYE, with the latest showing an improvement up to 13% in yield estimation accuracy.

This paper addresses the problem of automatic technology migration of analog IC designs. The proposed method introduces a new level of abstraction, for EDA tools addressing analog IC design, allowing a systematic and effortless adaption of a design to a new technology. The new abstraction level is based on generic cell libraries, which includes topology and testbenches descriptions for specific circuit classes. In addition to technology independence, reusing the testbenches when adding new topologies for the already implemented circuit classes also improves design productivity. The new method is implemented and tested using a state-of-the-art multi-objective multi-constraint circuit-level optimization tool for circuit sizing, and is validated for the design and optimization of continuous-time comparators, including technology migration between two different design nodes, respectively, XFAB 350 nm technology and ATMEL 150 nm SOI technology.

This paper presents a thermal-aware floorplaning tool for integrated MOSFET power stages. It generates area and power optimized transistors, automatically complying with design rules. The tool also creates placement solutions of power stages, optimizing for area, wire-length and temperature spread. The tool creates technology independent layouts, and directly export designs into GDSII format, allowing complete independence from IC design platforms. A brief comparison of floorplanning techniques, embedded in this tool, is presented for several generally known benchmarks. The device layout and thermal-aware floorplaning capabilities are demonstrated and compared with manual designs of a half-bridge power stage for a Class-D amplifier, and a manually optimized device layout in a DC-DC buck converter stage - the tool results exhibit lower resistance and dynamic power losses while speeding-up the design flow by orders of magnitude.

This paper presents a multi-standard reconflgurable sigma-delta modulator, which is able to support the predictable standards of fourth generation of mobile communication systems (4G). Furthermore, the proposed architecture halves the number of required analog-to-digital converters in parallel receivers, by processing concurrently two different signals. The major design issues are outlined and operation modes are detailed. A system-level simulation is performed to demonstrate the feasibility of the presented solution. The modulator is implemented into switched-capacitor circuits and device level simulations demonstrate the performance of the converter.

An efficient use of macromodeling techniques is pointed out as an effective approach to improve the convergence and speed of the optimization process. The methodology presented in this paper is based on a learning scheme using Support Vector Machines(SVMs) that together with and an evolutionary strategy is used to create efficient models to estimate and optimize the performance parameters of analog and mixed-signal ICs. The SVM is used to identify the feasible design space regions while at the same time the evolutionary techniques are looking for the global optimum. Finally, the proposed optimization based methodology is demonstrated for the design of a well known class of CMOSoperational amplifier topologies. The efficiency of the proposed approach is compared with standard and modified genetic algorithm kernels.

New techniques for realizing CMOS logarithmic analog-to-digital (A/D) converters employing pipeline and algorithmic architectures are described. This is achieved by replacing the operations of subtraction/addition and multiplications in their linear counterparts by simple scaling operations in the logarithmic domain. Logarithmic pipeline A/D converters are more appropriate for high-frequency applications whereas logarithmic algorithmic A/D converters are particularly suitable for compact, low-cost designs. Examples are given to illustrate the proposed techniques.

This paper describes digitally-controlled analogue signal processing and conversion techniques based on a logarithmic current attenuator building block fully compatible with digital CMOS technology, and whose accuracy depends solely on the matching of transistors. Application examples given to illustrate the proposed techniques include logarithmic analogue-to-digital and digital-to-analogue conversion and automatic gain control, functions commonly used in various communications and instrumentations applications.>