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Jürgen Schnerr

dblp:19/2233 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 65% Electronic design automation · 35%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation › simulation › architectural simulation
cycle-accurate simulation
0.112008
High-performance timing simulation of embedded software · DAC 2008
Performance modeling and evaluation › simulation › analog and hybrid computer simulation
hybrid simulation
0.112008
High-performance timing simulation of embedded software · DAC 2008
Performance modeling and evaluation
simulation
0.112008
High-performance timing simulation of embedded software · DAC 2008
Electronic design automation
timing analysis
0.112008
High-performance timing simulation of embedded software · DAC 2008
Electronic design automation › hardware verification and test
hardware verification
0.012008
High-performance timing simulation of embedded software · DAC 2008
Electronic design automation › hardware simulation
systemc simulation
0.012008
High-performance timing simulation of embedded software · DAC 2008

Methods — techniques the papers use, named apart from their topics

static execution time analysis · 0.1source code instrumentation · 0.1
YearPublicationVenuePosition
2008 High-performance timing simulation of embedded software
abstract
This paper presents an approach for cycle-accurate simulation of embedded software by integration in an abstract SystemC model. Compared to existing simulation-based approaches, we present a hybrid method that resolves performance issues by combining the advantages of simulation-based and analytical approaches. In a first step, cycle-accurate static execution time analysis is applied at each basic block of a cross-compiled binary program using static pro-cessor models. After that, the determined timing information is back-annotated into SystemC for fast simulation of all effects that can not be resolved statically. This allows the consideration of data dependencies during run-time and the incorporation of branch pre-diction and cache models by efficient source code instrumentation. The major benefit of our approach is that the generated code can be executed very efficiently on the simulation host with approxi-mately 90 % of the speed of the untimed software without any code instrumentation.
Jürgen Schnerr, Oliver Bringmann 0001, Alexander Viehl, Wolfgang Rosenstiel
DAC1
2005 Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
abstract
The application of a cycle accurate binary translator for rapid prototyping of SoCs is presented. This translator generates code to run on a rapid prototyping system consisting of a VLIW processor and FPGAs. The generated code is annotated with information that triggers cycle generation for the hardware in parallel with the execution of the translated program. The VLIW processor executes the translated program whereas the FPGAs contain the hardware for the parallel cycle generation and the bits interface that adapts the bits of the VLIW processor to the SoC bits of the emulated processor core.
Jürgen Schnerr, Oliver Bringmann 0001, Wolfgang Rosenstiel
DATE1
2003 Instruction Set Emulation for Rapid Prototyping of SoCs
Jürgen Schnerr, Gunter Haug, Wolfgang Rosenstiel
DATE1