Understanding turbulence and mix in compressible flows is of fundamental importance to real-world applications such as chemical combustion and supernova evolution.The ability to run in three dimensions and at very high resolution is required for the simulation to accurately represent the interaction of the various length scales, and consequently, the reactivity of the intermixing species.Toward this end, we have carried out a very high resolution (over 8 billion zones) 3-D simulation of the Richtmyer-Meshkov instability and turbulent mixing on the IBM Sustained Stewardship TeraOp (SST) system, developed under the auspices of the Department of Energy (DOE) Accelerated Strategic Computing Initiative (ASCI) and located at Lawrence Livermore National Laboratory.We have also undertaken an even higher resolution proofof-principle calculation (over 24 billion zones) on 5832 processors of the IBM system, which executed for over an hour at a sustained rate of 1.05 Tflop/s, as well as a short calculation with a modified algorithm that achieved a sustained rate of 1.18 Tflop/s.The full production scientific simulation, using a further modified algorithm, ran for 27,000 timesteps in slightly over a week of wall time using 3840 processors of the IBM system, clocking a sustained throughput of roughly 0.6 teraflop per second (32-bit arithmetic).Nearly 300,000 graphics files comprising over three terabytes of data were produced and post-processed.The capability of running in 3-D at high resolution enabled us to get a more accurate and detailed picture of the fluidflow structure -in particular, to simulate the development of fine scale structures from the interactions of long-and short-wavelength phenomena, to elucidate differences between twodimensional and three-dimensional turbulence, to explore a conjecture regarding the transition from unstable flow to fully developed turbulence with increasing Reynolds number, and to ascertain convergence of the computed solution with respect to mesh resolution.

Compiler optimizations play a pivotal role in determining the run-time performance of an application. Performance improvements stem from path length reduction, efficient instruction selection, pipeline scheduling, and memory penalty minimization. This paper describes typical optimizations and highlights the mechanisms by which they improve performance. We categorize the described optimizations as basic, architecture specific, interprocedural, and source level. To accurately make trade-offs in the hardware design process, compiler/hardware interaction is essential in the early design stages.>

A standard technique for mapping a chromosome is to randomly select pieces, to use restriction enzymes to cut these pieces into fragments, and then to use the fragments for estimating the probability of overlap of these pieces. The authors describe a computational approach which has been used in the mapping of human chromosome 16 at Los Alamos National Laboratory. In particular, they describe 6-way and clustered implementations of an IBM Clustered Fortran program for detection of fragment overlap, with specific attention paid to problem partitioning, task structure, synchronization, and other factors which allow this type of code to perform well on a cluster of shared-memory multiprocessors. Measurements for one, six, and twelve processors for reduced problem sizes are included.>

At the present time substantial software, memory, and CPU cycle penalties are incurred in bridging the semantic gap between high-level language formatted output statements and I/O device capabilities. Because of this gap and in response to the rapidly expanding capability of VLSI microelectronic circuits, a dedicated I/O processor is proposed to off-load the inherent conversion and formatting task from the host computer. The research reported here investigated the feasibility, the architectural requirements, and the implementational considerations of a regular design methodology for a VLSI-based I/O formatter.