Analog circuit sizing is a high-cost process in terms of the manual effort invested and the computation time spent. With rapidly developing technology and high market demand, bringing automated solutions for sizing has attracted great attention. This paper presents APOSTLE, an asynchronously parallel optimization method for sizing analog transistors using Deep Neural Network (DNN) learning. This work introduces several methods to minimize real-time of optimization when the sizing task consists of several different simulations with varying time costs. The key contributions of this paper are: (1) a batch optimization framework, (2) a novel deep neural network architecture for exploring design points when the existed solutions are not always fully evaluated, (3) a ranking approximation method based on cheap evaluations and (4) a theoretical approach to balance between the cheap and the expensive simulations to maximize the optimization efficiency. Our method shows high real-time efficiency compared to other black-box optimization methods both on small building blocks and on large industrial circuits while reaching similar or better performance.

As circuits’ speed and frequency increase, fast and accurate capture of the details of the parasitics in metal structures, such as inductors and clock trees, becomes more critical. However, conducting high-fidelity 3D electromagnetic (EM) simulations within the design loop is very time consuming and computationally expensive. To address this issue, we propose a surrogate-based optimization methodology flow, namely multi-fidelity surrogate-based optimization with candidate search (MFSBO-CS), which integrates the concept of multi-fidelity to reduce the full-wave EM simulation cost in analog/RF simulation-based optimization problems. To do so, a statistical co-kriging model is adapted as the surrogate to model the response surface, and a parallelizable perturbation-based adaptive sampling method is used to find the optima. Within the proposed method, low-fidelity fast RC parasitic extraction tools and high-fidelity full-wave EM solvers are used together to model the target design and then guide the proposed adaptive sample method to achieve the final optimal design parameters. The sampling method in this work not only delivers additional coverage of design space but also helps increase the accuracy of the surrogate model efficiently by updating multiple samples within one iteration. Moreover, a novel modeling technique is developed to further improve the multi-fidelity surrogate model at an acceptable additional computation cost. The effectiveness of the proposed technique is validated by mathematical proofs and numerical test function demonstration. In this article, MFSBO-CS has been applied to two design cases, and the result shows that the proposed methodology offers a cost-efficient solution for analog/RF design problems involving EM simulation. For the two design cases, MFSBO-CS either reaches comparably or outperforms the optimization result from various Bayesian optimization methods with only approximately one- to two-thirds of the computation cost.

As device dimensions shrink into the nanometer range, power and performance constraints prohibit the longevity of traditional MOS devices in circuit design. FinFETs, a quasi-planar double-gated device, has emerged as a replacement. While flnFETs provide promising electrostatic characteristics, they have the potential to suffer from significant self heating. We study in this paper self heating in multi-fin devices. We first develop thermal models for an individual fin with flared channel extensions and for multi-fin devices. We analyze several fin geometric parameters (fin width, and (gate) length) and investigate how fin spacing, fin height, gate oxide thickness and gate height affect the maximum fin temperatures in rectangular and flared channel extensions. Our data derived from numerical simulation validates our findings. We develop a novel metric, metric for electro-thermal sensitivity (METS), for measuring device thermal robustness. We use the metric to investigate electro-thermal device sensitivities. The metric, while applied to finFETs in this paper, is general and can be applied to any type of device for which coupled electrical and thermal models exist. Our work is the first to address thermal issues within multi-fin devices and to develop a widely-applicable electro-thermal metric.

FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive current. We investigate in this paper gate sizing of finFET devices, and we provide a comparison with 32nm bulk CMOS. Wider finFET devices are built utilizing multiple parallel fins between the source and drain. Independent gating of the finFET's double gates allows significant reduction in leakage current. We perform temperature-aware circuit optimization by modeling delay using temperature-dependent parameters, and by imposing constraints that limit the maximum allowable number of parallel fins. We show that finFET circuits are superior in performance and produce less static power when compared to 32nm circuits.