This paper describes a non-volatile reprogrammable FPGA fabric, whose configuration data are provided directly by flash memory. The fabric is optimized for low-cost, low-power applications, leveraging the density of flash and the elimination of conventional configuration SRAM and its attendant static power. After surveying the necessary background on flash and its application to FPGAs, the 1T flash cell is described along with relevant novel aspects of the fabric architecture. The addition of a third level of switching between inter-cluster signals and logic inputs helps to reduce area and raise typical utilization above 95%. Despite the longer signal path, performance is maintained by synergism between the improved routing flexibility and extreme minimization of the fastest LUT input delay. Test cost is reduced by built-in circuits that can test all switches without reprogramming the flash memory. The fabric has been implemented in a 65nm CMOS embedded flash process.

In a cluster-based FPGA, the interconnect from external routing tracks and cluster feedbacks to the LUT inputs consumes significant area, and no consensus has emerged among different implementations (e.g., 1-level or 2-level). In this paper, we model this interconnect as a unified input interconnect block (IIB). We identify three types of IIBs and develop general combinatorial techniques to count the number of distinct functional configurations for them. We use entropy, defined as the logarithm of this count, to estimate an IIB's routing flexibility. This enables us to analytically evaluate different IIBs without the customary time-consuming place and route experiments. We show that both depopulated 1-level IIBs and VPR-style 2-level IIBs achieve high routing flexibility but lack area efficiency. We propose a novel class of highly efficient, yet still simple, IIBs that use substantially fewer switches with only a small degradation in routing flexibility. Experimental results verify the routability of these IIBs, and confirm that entropy is a good predictor of routability.

In a cluster-based FPGA, the interconnect from external routing tracks and cluster feedbacks to the LUT inputs consumes significant area, and no consensus has emerged among different implementations (e.g., 1-level or 2-level). In this paper, we model this interconnect as a unified input interconnect block (IIB). We develop general combinatorial techniques to count the number of distinct functional configurations of an IIB. We use entropy, defined as the logarithm of this count, to estimate an IIB's routing flexibility. This enables us to analytically evaluate different IIBs without the customary time-consuming place and route experiments. We show that both depopulated 1-level IIBs and VPR-style 2-level IIBs achieve high routing flexibility but lack area efficiency. We propose a novel class of highly efficient, yet still simple, IIBs that use substantially fewer switches (as few as 1/3) with only a small degradation in routing flexibility. Experimental results verify the routability of these IIBs, and confirm that entropy is a good predictor of routability.

A new reprogrammable FPGA architecture is described which is specifically designed to be of very low cost.It covers a range of 35K to a million usable gates.In addition, it delivers high performance and it is synthesis efficient.This architecture is loosely based on an earlier reprogrammable Actel architecture named ES.By changing the structure of the interconnect and by making other improvements, we achieved an average cost reduction by a factor of three per usable gate.The first member of the family based on this architecture is fabricated on a 2.54 standard 0.25~ CMOS technology with a gate count of up to 130K which also includes 36K bits of two port RAM.The gate count of this part is verified in a fully automatic design flow starting from a high level description followed by synthesis, technology mapping, place and route, and timing extraction.

The FPGA development is an extraordinarily complex task, involving many people working in architecture, chip design, software, marketing and production. Each tends to focus on their immediate task, and have their own measures of goodness for what they do, as well as very particular constraints relevant to their discipline. In this panel we will discuss these measures and constraints in an attempt to see how they succeed in transcending the artificial borders in each discipline.

Routing channels in a field-programmable gate array contain predefined wiring segments of various lengths. These may be connected to the pins of the gates or joined end-to-end to form longer segments by programmable switches. The segmented channel routing problem is formulated, and polynomial time algorithms are given for certain special cases. The general problem is NP-complete, but it can be adequately solved in practice. Experiments indicate that a segmented channel with judiciously chosen segment lengths may near the efficiency of a conventional channel.

An effective approach to two-dimensional compaction of VLSI circuit layouts is discussed. Active devices are described in terms of circular primitives called bubbles. The wires are treated topologically in that no geometric representation is used for them during compaction. This avoids expensive geometrical manipulations of the wires. Cells are compacted by moving bubbles one at a time along design rule preserving paths so as to minimize a cost function directly related to the size of the cell. Geometrical realizations of the wires are reconstructed at the end of the compaction process. The resulting routing has minimum wire length for each wire.>