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Cindy Eisner

dblp:19/3353 · DBLP profile ↗
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21ranked-venue papers
11as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Theory of computation · 13 · 6 first-authorSoftware engineering, systems software and programming languages · 10 · 6 first-authorSystems, architecture and hardware · 4 · 2 first-authorSecurity and privacy · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
7 papers
Logic in computer science · 58% Automata and formal languages · 25% Automated reasoning and model checking · 17%
Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 54% Energy-efficient computing · 30% Distributed systems · 13%

Topics — the 21 heaviest of 22, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Logic in computer science
temporal logic
0.252005
A topological characterization of weakness · PODC 2005
The Definition of a Temporal Clock Operator · ICALP 2003
Reasoning with Temporal Logic on Truncated Paths · CAV 2003
Energy-efficient computing
clock gating
0.112009
Resurrecting infeasible clock-gating functions · DAC 2009
Energy-efficient computing
power management
0.112009
Resurrecting infeasible clock-gating functions · DAC 2009
Distributed systems
compositional reasoning
0.112008
Functional Verification of Power Gated Designs by Compositional Reasoning · CAV 2008
Electronic design automation › hardware verification and test
functional verification
0.112008
Functional Verification of Power Gated Designs by Compositional Reasoning · CAV 2008
Electronic design automation › hardware verification and test
hardware verification
0.112008
Functional Verification of Power Gated Designs by Compositional Reasoning · CAV 2008
Automated reasoning and model checking
model checking
0.132003
Reasoning with Temporal Logic on Truncated Paths · CAV 2003
Efficient Detection of Vacuity in ACTL Formulaas · CAV 1997
RuleBase: Model Checking at IBM · CAV 1997
Logic in computer science
semantics
0.112005
A topological characterization of weakness · PODC 2005
Logic in computer science
topological characterization
0.112005
A topological characterization of weakness · PODC 2005
Electronic design automation › hardware verification and test
formal verification
0.022000
A methodology for formal design of hardware control with application to cache coherence protocols · DAC 2000
RuleBase: An Industry-Oriented Formal Verification Tool · DAC 1996
Electronic design automation
hardware verification and test
0.022000
A methodology for formal design of hardware control with application to cache coherence protocols · DAC 2000
RuleBase: An Industry-Oriented Formal Verification Tool · DAC 1996
Logic in computer science › temporal logic
temporal logic reasoning
0.012003
Reasoning with Temporal Logic on Truncated Paths · CAV 2003
Logic in computer science › formal specification
specification language
0.012001
The Temporal Logic Sugar · CAV 2001
Electronic design automation › logic synthesis › sequential circuit optimization
clock gating synthesis
0.012009
Resurrecting infeasible clock-gating functions · DAC 2009
Electronic design automation
logic synthesis
0.012009
Resurrecting infeasible clock-gating functions · DAC 2009
Electronic design automation
high-level synthesis
0.012000
A methodology for formal design of hardware control with application to cache coherence protocols · DAC 2000
Automated reasoning and model checking › model checking
symbolic model checking
0.011997
RuleBase: Model Checking at IBM · CAV 1997
Automated reasoning and model checking › model checking › temporal logic model checking
vacuity detection
0.011997
Efficient Detection of Vacuity in ACTL Formulaas · CAV 1997
Logic in computer science
formal semantics
0.012003
The Definition of a Temporal Clock Operator · ICALP 2003
Memory systems
cache coherence
0.012000
A methodology for formal design of hardware control with application to cache coherence protocols · DAC 2000
Memory systems › cache coherence
cache coherence protocol
0.012000
A methodology for formal design of hardware control with application to cache coherence protocols · DAC 2000

Methods — techniques the papers use, named apart from their topics

automata theory · 0.2timing-aware approximation · 0.1clustering · 0.1compositional reasoning · 0.1
YearPublicationVenuePosition
2018 Accurate Malware Detection by Extreme Abstraction
abstract
Modern malware applies a rich arsenal of evasion techniques to render dynamic analysis ineffective. In turn, dynamic analysis tools take great pains to hide themselves from malware; typically this entails trying to be as faithful as possible to the behavior of a real run. We present a novel approach to malware analysis that turns this idea on its head, using an extreme abstraction of the operating system that intentionally strays from real behavior. The key insight is that the presence of malicious behavior is sufficient evidence of malicious intent, even if the path taken is not one that could occur during a real run of the sample. By exploring multiple paths in a system that only approximates the behavior of a real system, we can discover behavior that would often be hard to elicit otherwise. We aggregate features from multiple paths and use a funnel-like configuration of machine learning classifiers to achieve high accuracy without incurring too much of a performance penalty. We describe our system, TAMALES (The Abstract Malware Analysis LEarning System), in detail and present machine learning results using a 330K sample set showing an FPR (False Positive Rate) of 0.10% with a TPR (True Positive Rate) of 99.11%, demonstrating that extreme abstraction can be extraordinarily effective in providing data that allows a classifier to accurately detect malware.
Fady Copty, Matan Danos, Orit Edelstein, Cindy Eisner, Dov Murik, Benjamin Zeltser
ACSAC4
2014 Safety and Liveness, Weakness and Strength, and the Underlying Topological Relations
abstract
We present a characterization that shows what it means for a formula to be a weak or strong version of another formula. We show that the weak version of a formula is not the same as Alpern and Schneider's safety component, but can be achieved by taking the closure in the Cantor topology over an augmented alphabet in which every formula is satisfiable. The resulting characterization allows us to show that the set of semantically weak formulas is exactly the set of nonpathological safety formulas. Furthermore, we use the characterization to show that the original versions of the ieee standard temporal logics psl and sva are broken, and we show that the source of the problem lies in the semantics of the sere intersection and fusion operators. Finally, we use the topological characterization to show the internal consistency of the alternative semantics adopted by the latest version of the psl standard.
Cindy Eisner, Dana Fisman, John Havlicek
ACM Trans. Comput. Log.1
2013 Relative Equivalence in the Presence of Ambiguity
Oshri Adler, Cindy Eisner, Tatyana Veksler
CAV2
2009 Resurrecting infeasible clock-gating functions
abstract
In this paper we consider the problem of exploiting infeasible clock gating functions. Analysis of industrial designs reveals a large margin of potential for power saving based on clock gating functions that initially appear to be useless due to timing violation or excessive power consumption. We propose two optimization techniques for resurrecting such functions that can be used as a generic post-processing phase in an automatic clock gating tool. The first provides timing-aware approximation and the second aims at generating large gating domains by clustering similar clock gating functions. Our experimental results show that the combination of these two techniques yields an additional power saving of up to 78% in industrial designs.
Eli Arbel, Cindy Eisner, Oleg Rokhlenko
DAC2
2009 Functional verification of power gated designs by compositional reasoning
Cindy Eisner, Amir Nahir, Karen Yorav
Formal Methods Syst. Des.1
2008 Functional Verification of Power Gated Designs by Compositional Reasoning
Cindy Eisner, Amir Nahir, Karen Yorav
CAV1
2008 Augmenting a Regular Expression-Based Temporal Logic with Local Variables
abstract
The semantics of temporal logic is usually defined with respect to a word representing a computation path over a set of atomic propositions. A temporal logic formula does not control the behavior of the atomic propositions, it merely observes their behavior. Local variables are a twist on this approach, in which the user can declare variables local to the formula and control their behavior from within the formula itself. Local variables were introduced in 2002, and a formal semantics was given to them in the context of SVA, the assertion language of SystemVerilog, in 2004. That semantics suffers from several drawbacks. In particular, it breaks distributivity of the operators corresponding to intersection and union. In this paper we present a formal semantics for local variables that solves that problem and others, and compare it to the previous solution.
Cindy Eisner, Dana Fisman
FMCAD1
2007 PSL for Runtime Verification: Theory and Practice
Cindy Eisner
RV1
2005 A topological characterization of weakness
abstract
We are interested in the relation between weak and strong temporal operators. We would like to find a characterization that shows what it means for an operator to be the weak or strong version of another operator, or more generally for a formula to be a weak or strong version of another formula. We show that the weak version of a formula is not the same as Alpern and Schneider's safety component. By working over an extended alphabet, we show that their topological characterization of safety can be adapted to obtain a topological characterization of weakness. We study the resulting topology and the relations between weak and strong formulas. Finally, we apply the method to show the internal consistency of a logic containing both weak and strong versions of regular expressions.
Cindy Eisner, Dana Fisman, John Havlicek
PODC1
2005 Formal verification of software source code through semi-automatic modeling
Cindy Eisner
Softw. Syst. Model.1
2003 Reasoning with Temporal Logic on Truncated Paths
Cindy Eisner, Dana Fisman, John Havlicek, Yoad Lustig, Anthony McIsaac, David Van Campenhout
CAV1
2003 The Definition of a Temporal Clock Operator
Cindy Eisner, Dana Fisman, John Havlicek, Anthony McIsaac, David Van Campenhout
ICALP1
2003 Model Checking at IBM
Shoham Ben-David, Cindy Eisner, Daniel Geist, Yaron Wolfsthal
Formal Methods Syst. Des.2
2002 Using symbolic CTL model checking to verify the railway stations of Hoorn-Kersenboogerd and Heerhugowaard
Cindy Eisner
Int. J. Softw. Tools Technol. Transf.1
2001 The Temporal Logic Sugar
Ilan Beer, Shoham Ben-David, Cindy Eisner, Dana Fisman, Anna Gringauze, Yoav Rodeh
CAV3
2001 On the Effective Deployment of Functional Formal Verification
Yael Abarbanel-Vinov, Neta Aizenbud-Reshef, Ilan Beer, Cindy Eisner, Daniel Geist, Tamir Heyman, Iris Reuveni, Eran Rippel, Irit Shitsevalov, Yaron Wolfsthal, Tali Yatzkar-Haham
Formal Methods Syst. Des.4
2001 Efficient Detection of Vacuity in Temporal Model Checking
Ilan Beer, Shoham Ben-David, Cindy Eisner, Yoav Rodeh
Formal Methods Syst. Des.3
2000 A methodology for formal design of hardware control with application to cache coherence protocols
abstract
We propose a methodology for developing hardware control. In addition to the usual distinction between control and data path, a further distinction within the control code is made between algorithmic code and bookkeeping code. The high level specification describes the algorithmic code in an object-oriented st yle, is executable, formally verified, and automatically translated into HDL, thus giving hardware which is by construction equivalen t to its specification. We discuss the application of this methodology as it is used in product development of cache coherence protocols.
Cindy Eisner, Irit Shitsevalov, Russ Hoover, Wayne G. Nation, Kyle L. Nelson, Ken Valk
DAC1
1997 RuleBase: Model Checking at IBM
Ilan Beer, Shoham Ben-David, Cindy Eisner, Daniel Geist, Leonid Gluhovsky, Tamir Heyman, Avner Landver, P. Paanah, Yoav Rodeh, G. Ronin, Yaron Wolfsthal
CAV3
1997 Efficient Detection of Vacuity in ACTL Formulaas
Ilan Beer, Shoham Ben-David, Cindy Eisner, Yoav Rodeh
CAV3
1996 RuleBase: An Industry-Oriented Formal Verification Tool
abstract
RuleBase is a formal verification tool, developed by the IBM Haifa Research Laboratory. It is the result of three years of experience in practical formal verification of hardware which, we believe, has been a key factor in bringing the tool to its current level of maturity. We present the tool, including several unique features, and summarize our usage experience.
Ilan Beer, Shoham Ben-David, Cindy Eisner, Avner Landver
DAC3