Small-message aggregation is critical for scaling irregular, communication intensive applications in high-performance computing. In this paper, contrary to conventional wisdom, we present the first systematic study showing that memory contention, not network bandwidth, is the dominant bottleneck in message aggregation runtimes. Using the state-of-the-art conveyors library as our reference implementation, we conducted extensive experiments on HPC systems featuring Slingshot 11 and InfiniBand interconnects, scaling to 16k cores (256 nodes) and processing 10s–100s GB of data. Our measurements reveal that interference between user data and aggregation buffers drives LLC miss rates to 77%, inflating memory costs by 2–3× over the algorithmic baseline. Consequently, we advocate for dedicated near-memory subsystems to improve the scalability and performance of message aggregation runtimes. This paper also demonstrates up to an order of magnitude higher latency for conveyor termination compared to a traditional HPC barrier, and it examines the impact of communication context isolation and the critical challenge of programmability.

This paper describes a new asynchronous algorithm and implementation for the problem of$\boldsymbol{k}$-mer counting$(\text{KC})$, which concerns quantifying the frequency of length$k$substrings in a DNA sequence. This operation is common to many computational biology workloads and can take up to 77 % of the total runtime of de novo genome assembly. The performance and scalability of the current state-of-the-art distributed-memory KC algorithm are hampered by multiple rounds of Many-To-Many collectives. Therefore, we develop an asynchronous algorithm (DAKC) that uses fine-grained, asynchronous messages to obviate most of this global communication while utilizing network bandwidth efficiently via custom message aggregation protocols. DAKC can perform strong scaling up to 256 nodes (512 sockets$/ 6 ~\mathrm{K}$cores) and can count$k$-mers up to$9 \times$faster than the state-of-the-art distributed-memory algorithm, and up to$100 \times$faster than the shared-memory alternative. We also provide an analytical model to understand the hardware resource utilization of our asynchronous KC algorithm and provide insights on the performance.

With the growing complexity of modern internet networks, we introduce a distributed, asynchronous, and scalable algorithm tailored for determining the centrality and importance of various levels of the global internet network topology at a massive scale. By utilizing triangle formations and neighborhood densities in these complex networks, our algorithm provides valuable insights into the structural importance of individual nodes and the intricate relationships among interconnected entities. Focusing on the global internet's prime components — routers, IP addresses, and Autonomous Systems — the algorithm provides a scalable solution extending to the global internet infrastructure, datacenters, cloud networks, and private networks. By taking advantage of the parallelism, distributed processing, efficient communication, and fine-grained asynchronous execution through an Actor-based programming system, our algorithm is capable of efficiently processing and performing rapid computations on large-scale internet networks. We perform scalability studies on the NERSC Perlmutter supercomputer and the Georgia Tech HPC PACE cluster using three large-scale real-world network datasets and one large-scale synthetic network dataset, achieving up to 91.7% parallel efficiency scaling out to 2K cores and reducing execution time from 5.7 hours to 18.3 seconds, while performing 105.4× better on average compared to related approaches. Our research contributes significantly to facilitating enhanced network management, fault tolerance and resilience, and security, but as well to improving overall network stability, reducing latency, and optimizing energy consumption across the vast internet network devices environment.

On massively parallel computing systems, applications involving many small message transfers suffer from degradation in performance and scalability. Typically, applications built on OpenSHMEM, Chapel, and Unified Parallel C (UPC) suffer due to poor network message rates, causing under-utilization of network bandwidth. In past work, a memory-efficient aggregation library called Conveyors was developed to address this issue in the PGAS (Partitioned Global Address Space) based SPMD (Single Program Multiple Data) model offering flexible APIs and contracts. The Conveyors library has been used by multiple HPC frameworks, including Chapel, HABU, and HClib. We scope this paper as an investigative study of Conveyors at a time where none of the profilers, such as score-p, Intel Vtune, and CrayPat, measure asynchronous OpenSHMEM calls. Specifically, we conduct a series of experiments and identify cases where certain one-to-one/all-to-all communication patterns can lead to bottlenecks due to specific design choices made by Conveyors.

Influence maximization (IM) is the problem of finding the k most influential nodes in a graph. We propose distributed-memory parallel algorithms for the two main kernels of a state-of-the-art implementation of one IM algorithm, influence maximization via martingales (IMM). The baseline relies on a bulk-synchronous parallel approach and uses replication to reduce communication and achieve approximate load balance, at the cost of synchronization and high memory requirements. By contrast, our method fully distributes the data, thereby improving memory scalability, and uses fine-grained asynchronous parallelism to improve network utilization and the cost of doing more communication. We show our design and implementation can achieve up to $29.6 \times$ speedup over the MPI-based state-of-the-art on synthetic and real-world network graphs. Moreover, ours is the first implementation that can run IMM to find influencers in the ‘twitter’ graph (41M nodes and 1.4B edges) in 200 seconds using 8 K CPU cores of NERSC Perlmutter supercomputer.

In this work-in-progress research paper, we make the case for using Rust to develop applications in the High Performance Computing (HPC) domain which is critically dependent on native C/C++ libraries. This work explores one example of Safe HPC via the design of a Rust interface to an existing distributed C++ Actors library. This existing library has been shown to deliver high performance to C++ developers of irregular Partitioned Global Address Space (PGAS) applications.

Non-volatile Main Memories (NVMs) offer a promising way to preserve data persistence and enable computation recovery in case of failure. While the use of NVMs can significantly reduce the overhead of failure recovery, which is the case with High-Performance Computing (HPC) kernels, rewriting existing programs or writing new applications for NVMs is non-trivial. In this article, we present a compiler-support that automatically inserts complex instructions into kernels to achieve NVM data-persistence based on a simple programmer directive. Unlike checkpointing techniques that store the whole system state, our technique only persists user-designated objects as well as some parameters required for safe recovery such as loop induction variables. Also, our technique can reduce the number of data transfer operations, because our compiler coalesces consecutive memory-persisting operations into a single memory transaction per cache line when possible. Our compiler-support is implemented in the LLVM tool-chain and introduces the necessary modifications to loop-intensive computational kernels (e.g., TMM, LU, Gauss, and FFT) to force data persistence. The experiments show that our proposed compiler-support outperforms the most recent checkpointing techniques while its performance overheads are insignificant.

Recently, it has become possible to easily use video teaching materials in lectures and exercises using high-performance information terminals. In this study, we design and develop playback functions for lecture videos as learning support using a learning management system. The main feature of the proposed system generates keywords from handwritten characters and lecture speech so that learners can search for playback positions related to keywords. Additionally, it becomes possible to create a highly maintainable system in a short development period using speech recognition and still-image recognition functions available on the internet. In this paper, we describe our prototype implementation and present the results of our initial evaluation. The results demonstrate that, regarding the playback of a lecture video, it is possible to use the keyword search function 20–40 min after the lecture video is released. Moreover, we implemented a playback system using a block function on Moodle so that other teaching material in the course could be viewed simultaneously.

GPUs can enable significant performance improvements for certain classes of data parallel applications and are widely used in recent computer systems. However, GPU execution currently requires explicit low-level operations such as 1) managing memory allocations and transfers between the host system and the GPU, 2) writing GPU kernels in a low-level programming model such as CUDA or OpenCL, and 3) optimizing the kernels by utilizing appropriate memory types on the GPU. Because of this complexity, in many cases, only expert programmers can exploit the computational capabilities of GPUs through the CUDA/OpenCL languages. This is unfortunate since a large number of programmers use high-level languages, such as Java, due to their advantages of productivity, safety, and platform portability, but would still like to exploit the performance benefits of GPUs. Thus, one challenging problem is how to utilize GPUs while allowing programmers to continue to benefit from the productivity advantages of languages like Java. This paper presents a just-in-time (JIT) compiler that can generate and optimize GPU code from a pure Java program written using lambda expressions with the new parallel streams APIs in Java 8. These APIs allow Java programmers to express data parallelism at a higher level than threads and tasks. Our approach translates lambda expressions with parallel streams APIs in Java 8 into GPU code and automatically generates runtime calls that handle the low-level operations mentioned above. Additionally, our optimization techniques 1) allocate and align the starting address of the Java array body in the GPUs with the memory transaction boundary to increase memory bandwidth, 2) utilize read-only cache for array accesses to increase memory efficiency in GPUs, and 3) eliminate redundant data transfer between the host and the GPU. The compiler also performs loop versioning for eliminating redundant exception checks and for supporting virtual method invocations within GPU kernels. These features and optimizations are supported and automatically performed by a JIT compiler that is built on top of a production version of the IBM Java 8 runtime environment. Our experimental results on an NVIDIA Tesla GPU show significant performance improvements over sequential execution (127.9 × geometric mean) and parallel execution (3.3 × geometric mean) for eight Java 8 benchmark programs running on a 160-thread POWER8 machine. This paper also includes an in-depth analysis of GPU execution to show the impact of our optimization techniques by selectively disabling each optimization. Our experimental results show a geometric-mean speed-up of 1.15 × in the GPU kernel over state-of-the-art approaches. Overall, our JIT compiler can improve the performance of Java 8 programs by automatically leveraging the computational capability of GPUs.

This paper describes an avoidance behavior from unknown external forces for a biped walking vehicle. To distinguish between external forces from passenger and those from environments, we use the data of a force sensor mounted on foot, and external forces are estimated from ZMP errors. To guarantee a walking stability, the waist position is adjusted to match the measured ZMP to the reference ZMP, and the position of landing foot is adjusted so that the waist trajectory does not diverge. By implementing the developed method on the human-carrying biped robot, the robot realized a stable walk under unknown external forces from environments. When pushing the robot stepping, the robot moved backward and moved away from the generation source of external forces about 400 mm. When pushing the robot walking forward, the robot stopped going forward and prevented from coming closer to the generation source of external forces. We confirmed the effectiveness of the proposed control through these experiments.

Many researchers have studied on walking stability controls for biped robots. Most of them are highly accurate acceleration controls based on the mechanics model of the robot. However, the control algorithms are difficult to be applied to human-carrying biped robots due to modeling errors. In the previous report, we proposed the landing pattern modification method, but it had a problem that a foot landing impact increased when a walking speed became fast. So, we propose a new terrain-adaptive control that can reduce a landing- impact force. To increase a concave terrain adaptation, we set a target landing position beneath a reference level. To reduce the landing-impact force, we change the position gain control value to a small value at a swing phase. Moreover, we set landing-foot speed at zero after detecting a foot-landing by the force sensor mounted on a foot. To follow uneven terrain, a virtual spring is installed to the vertical direction after detecting a foot-landing on a ground, and a virtual compliance control is applied to the roll and pitch axes. In a stable walk while carrying a 65 kg human on uneven terrain, the new control method decreased the landing-impact force than the previous terrain-adaptive control.

A heterogeneous multi-core processor (HMCP) architecture, which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption with the support of a parallelizing compiler, was developed. The evaluation was performed using an MP3 audio encoder on a simulator that accurately models the HMCP. It showed that 16-frame encoding on the HMCP with four CPUs and four ACCs yielded 24.5-fold speed-up of performance against sequential execution on one CPU. Furthermore, power saving by the compiler reduced energy consumption of the encoding to 0.17 J, namely, by 28.4%.

Many control methods have been studied on the assumption that the feet of biped robots contact the ground with four points. However, it is difficult for almost all of such biped robots to maintain four-point contact on uneven terrains because they have rigid and flat soles. In order to solve the problem, foot mechanisms should be studied. In 2003, we developed WS-1R (Waseda Shoes - No.1 Refined) which is able to maintain four-point contact. However, it is difficult to deal with the concave or convex ground because of the problems of the contact detection and sideways slip. So, WS-5 (Waseda Shoes - No.5) has been developed. To avoid the slip of the foot, a cam-slider locking system consisting of a solenoid and a cam is constructed and installed at the foot. Also, linear encoders are employed to measure the position of the foot sliders. Through walking experiments on uneven terrains, the effectiveness of WS-5 is confirmed.

Previously, the realization of ascending and descending stairs and landing pattern modification control by WL-16RII were reported. However, it is difficult to use the landing pattern modification control when ascending stairs, because of the insufficient stroke of linear actuators. In this report, the design of a double stage linear actuator with a larger expansion and contraction ratio is described. The new linear actuators developed have been installed in WL-16RII, and several experiments were conducted. Through experiments involving walking with a wide step length and ascending a stair with landing pattern modification control, the effectiveness of the actuator developed is confirmed.

This paper describes how to compensate unknown external forces caused by a rider's motion of a biped walking vehicle. When external forces act on a robot's waist, the waist is accelerated so that a measured ZMP may be equal to a reference ZMP. To inhibit the divergence of the waist motion, the reference ZMP is varied inside a support polygon. However, if a large external force acts on a robot, the waist trajectory does not converge by only controlling a reference ZMP. So, ZMP trajectory is varied by changing a foot-landing point. Using the proposed control method, WL-16RIV (Waseda Leg-No. 16 Refined IV) achieved a stable human-carrying walking under unknown external forces which exert forward and sideways on the robot's waist. Through various walking experiments, the effectiveness of the proposed method was confirmed.

Many researchers have been studying on walking control methods for biped robots. However, the effectiveness of these control methods was not verified in outdoor environments such as pedestrian roads and gravel roads. In this paper, a landing pattern modification method adaptable to uneven terrain in a real environment is proposed which is based on a predictive attitude compensation control and a nonlinear compliance control. This method does not require any other sensors except force sensors. Also, a new biped foot system is described which can form larger support polygons on uneven terrain than conventional biped foot systems. Using the modification method and the foot system, WL-16RII (Waseda Leg-No.16 Refined II) achieved a stable walk on bumpy terrain with 20 mm height and 10 degrees inclination. Furthermore, a stable dynamic walk was realized on a paved road, when a human rode it. Through various walking experiments, the effectiveness of the method was confirmed

This paper describes a passive dynamic model of passenger for a biped walking vehicle. The walking pattern generation that enables stable walking even if passenger sits naturally is also described. The model consists of lower-limbs part assumed to be fixed to the robot, and the upper body assumed to be 1 particle with 2 DOF mounted on the seat via 2 springs and dampers. The parameters are identified through waist shaking experiments by using a force-torque sensor under the seat. The walking pattern generation method involves the proposed model being built onto a strict model of the robot, and through iteration computation, a stable walking pattern is generated. The effectiveness of the proposed method is confirmed through experiments