Physical Unclonable Functions (PUFs) exploit the manufacturing process variations inherent in silicon-based chips to generate unique secret keys. Although PUFs are supposed to be unclonable or unbreakable, researchers have found that they are vulnerable to machine learning (ML) attacks. In this article, we analyze the vulnerability of different FPGA-based Ring Oscillator PUFs (ROPUFs) to machine learning attacks. The challenge-response pairs (CRPs) data obtained from different ROPUFs is trained using different machine learning algorithms. From the study, it is found that the Artificial Neural Network (ANN) models can be used to train the ROPUFs with a training accuracy of 99.9% and a prediction accuracy of 62% when 5,000 CRPs are used for a challenge-response ROPUF. In this article, we assume a realistic situation where a small set of the CRP dataset (approximately 15% maximum) is unscrupulously obtained by the hacker. A prediction accuracy of 62% makes the PUF vulnerable to machine learning attacks. Therefore, a secondary goal of this article is the design of a ROPUF capable of thwarting machine learning modeling attacks. The modified XOR-inverter ROPUF drastically reduces the prediction accuracy from 62% to 13.1%, thus making it increasingly difficult for hackers to attack the ROPUF.

Recently, electronic industries have been facing an increased amount of hardware counterfeits. These counterfeit components, when assembled into a product or a system, can not only jeopardize performance and reliability but also create safety issues. Physical Unclonable Function (PUF) provides means to enhance physical security of Integrated Circuits (IC) against piracy and unauthorized access. The proposed design illustrates the feasibility of using self-timed ring oscillators as a novel approach towards PUF implementation for FPGA authentication. The proposed Self-Timed Ring Oscillator PUF (STRO-PUF) consists of two groups of identically laid-out self-timed ring oscillators. Inputs to the PUF are given through a challenge generator, which selects two self-timed ring oscillators from each group. Outputs of oscillators are fed to multiplexers of corresponding groups. Self-timed ring oscillators exploit the inherent features of random process variations by producing varying frequencies. These unpredictable variations in frequencies are captured using frequency comparator, which generates a output bit. A unique set of output bits , or response is generated for each set of input bits, or challenge. This unique Challenge Response Pair (CRP) is used in identifying a particular device. Frequencies generated from these oscillators are read through a logic analyzer. The varying frequencies observed from all the oscillators mapped across different regions of FPGAs range from 16.234 MHz to 125 MHz with the average frequency of 101.446 MHz. Experimental result shows the uniqueness for the PUF response is 49.92% which is very close to the desired 50% factor.

This paper presents a novel design of a Field Programmable Gate Array (FPGA) based on Quantum-dot Cellular Automata (QCA) technology. QCA is a transistorless emerging technology based on Coulombic repulsion. It is being explored as one of the alternative technologies which may replace CMOS in the future. In this work, QCA based nano FPGAs are designed and simulated. The designs of the Configurable Logic Block (CLB) and the Programmable Switch Matrix (PSM) are first developed separately and then integrated together to form a complete QCA based FPGA. The circuit components are designed to take full advantage of the unique features of QCA technology. It is observed that the proposed circuits have less latency and occupy less area compared to earlier designs. Also, to the best of our knowledge, this is the first integrated design of a QCA based FPGA which includes both CLBs and PSMs. The FPGA is designed and simulated using the QCADesigner tool.

The threat of digital counterfeiting and forgery of integrated circuits is growing at an alarming rate. At the same time, the functionalities of integrated circuits are becoming much more complex. This paper presents a design for cryptographic applications using Physically Unclonable Functions (PUFs) that can be implemented on an FPGA taking advantage of its unique architecture. The first part of the research involves development of techniques for the generation of uniquely distinguishable responses from ROPUFs taking advantage of the unique architecture of the FPGA and the latter part involves development of error correction technique using Artificial Neural Networks. The proposed design is implemented on several Xilinx Spartan FPGAs and the Hamming distances for the responses are computed and analyzed. The uniqueness of the responses is found to be 49.0625%. It is also found that the results of the proposed ECC also prove to be computationally efficient than the conventional BCH codes.

This paper introduces a modeling scheme that takes the effects of shading patterns on the output power of a solar cell array using MATLAB. A module consisting of an array of parallel connected strings of solar cells is considered for analysis under shading conditions. The model finds the solutions of complex nonlinear equations of solar cell under random illumination conditions. The approach has been extended to special shading cases. Additionally the effect of load resistance variation on the maximum power point under different shading patterns is performed.

Access control is a means by which the ability to access the system is explicitly enabled or restricted in some way. Access control system enables an authority to control access to areas and resources in a given physical facility or computer-based information system. In Role-based Access Control (RBAC) model, access to resources is based on the role of the user in an organization. Previous RBAC models have encountered various problems in meeting the growing and diverse security needs of the organizations. Hence, we propose Isolation Enabled Role-based Access Control (I-RBAC) model. The basic idea of our model is to incorporate the isolation concepts into the NIST (National Institute of Standards and Technology) RBAC model such that it can be applied in a broader domain. In I-RBAC, the operation on an object by the role is executed inside isolation environment if the role or the operation is predefined to be isolated. Typical roles include inexperienced personnel (such as intern doctors) and delegatee. At the end of each session a security check for accumulated modifications will notify the user about the consistency of the environments. Evaluation of the implementation of the prototype on a Health Care System demonstrates the effectiveness of I-RBAC model. The key idea is to ensure system availability at all times for all the roles, while simultaneously ensuring the system integrity and security. Another main advantage is that, it would be a cost-effective alternative to building a separate RBAC system to enable otherwise disallowed accesses, such as the training roles.

As CMOS technology reaches its limitations during the next decade, novel nano electronic devices like Carbon Nano Tubes, Single Electron Transistors, Quantum Cellular Automata, and Spin Transistors are being explored as future alternatives to CMOS devices. This research focuses on Quantum Cellular Automata (QCA) as a viable technology for future FPGA devices. Small device size, ultra low power consumption, and extremely high device operation speeds are some of the outstanding features of QCA which makes it attractive. In this research paper, modeling, implementation, and successful simulation of a CLB slice for a nano quantum FPGA in QCA technology is discussed. The design is modeled using standard QCA cells with multiple layers for reliable interconnect crossovers. The designs are implemented and simulated using the QCA Designer software tool.

With the scaling of submicron device dimensions, the current density and the temperature of interconnects have increased many folds leading to component failure due to electromigration. This paper analyzes the effect of electromigration failures in the interconnect of SRAM-based Field Programmable Gate Arrays (FPGAs). The Mean Time to Failure (MTF) of interconnects is calculated for different benchmark circuits and the variation of current density with MTF is observed. A frequency domain Built-in-Self Test (BIST) scheme is proposed which employs Arithmetic Fourier Transform (AFT) to obtain the spectrum of control sequences to detect weak logic signals.

This paper presents a unique scheme for testing and locating multiple stuck at faults in the embedded RAM modules of SRAM-based FPGAs. The RAM modules are tested using the MATS++ algorithm. The interconnection scheme makes it possible to test all the cells within the RAM modules in the FPGA in just one test configuration. A diagnosis scheme capable of locating the faulty RAM cell and the CLB in which it is located is also developed.Considerable research in the area of testing the LUT/RAM modules for SRAM based FPGAs has been done earlier. However, the solutions proposed are not optimal as they require N test configurations to test an N input RAM module. One such solution proposes a Pseudo Shift Register (PSR) interconnection scheme using the shifted MATS++ algorithm. It is possible to test all the RAM modules in an FPGA in one test configuration using this approach. However, although this scheme can detect the faulty cell in the RAM modules under test, it does not have the capability of locating the faulty CLB in which the RAM modules are located. In other words, the scheme assumes that the faulty CLB is known. This drawback is eliminated in the scheme presented in this paper by using a unique interconnection of CLBs in the form of a chain. In addition, the proposed interconnection scheme also reduces the testing time by approximately half as compared to the time taken by earlier schemes. The FPGA is modeled in VHDL at the equivalent gate level and the simulations results are generated using ModelSim.

This paper explores the built-in self test (BIST) concepts to test the configurable logic blocks (CLBs) of static RAM (SRAM) based FPGAs using Java Bits (JBits). The proposed technique detects and diagnoses single and multiple stuck-at faults in the CLBs while significantly reducing the time taken to perform the testing. Previous BIST approaches for testing FPGAs use traditional CAD tools which lack control over configurable resources, resulting in the design being placed on the hardware in a different way than intended by the designer. In this paper, the design of the logic BIST architecture is done using JBits 2.8 software for Xilinx Virtex family of devices. The test requires seven configurations and two test sessions to test the CLBs. The time taken to generate the entire BIST logic in both the sessions is approximately 77 seconds as compared with several minutes to hours in traditional design flow.

In this paper, the design and analysis of a mesh-type systolic array architecture for computing the Single Linkage (SLINK) algorithm is presented. This algorithm is frequently used in hierarchical clustering applications. However, since the algorithm is iterative in nature, it takes considerable CPU time for processing. This makes the algorithm unattractive for real-time applications. The systolic array, described in this paper, increases the speed of computation of the algorithm.>