The demand for virtual private networks (VPNs) that provide confidentiality, integrity, and authenticity of communications is growing every year. IPsec is one of the oldest and most widely used VPN protocols, implemented between the internet protocol (IP) layer and the data link layer of the Linux kernel. This implementation method, known as bump-in-the-stack, has the advantage of being able to transparently apply IPsec to traffic without changing the application. However, its throughput efficiency (Gbps/core) is worse than regular Linux communication. Therefore, we chose the bump-in-the-wire (BITW) architecture, which handles IPsec in hardware separate from the host. Our proposed BITW architecture consists of inline cryptographic accelerators implemented in field-programmable gate arrays and a programmable switch that connects multiple such accelerators. A VPN gateway implemented with our architecture is transparent and improves the throughput efficiency by 3.51 times and power efficiency by 3.40 times over a VPN gateway implemented in the Linux kernel. It also demonstrates excellent scalability, and has been confirmed to scale to a maximum of 386.24 Gbps per tunnel, exceeding state-of-the-art technology in maximum throughput and efficiency per tunnel. In multiple-tunnels use cases, the proposed architecture improves the energy efficiency by 2.49 times.

VTA-NIC Chip ArchitectureWe aim to achieve DL inference serving (DLIS) without CPU interference.We integrate hardware data paths as a NIC (Network Interface Card), a REST API parser/deparser and multiple VTAs (Versatile Tensor Accelerators).ConfigurationVTA-NICProcess node16 nm FinFET @Xilinx FPGANumber of Cores8 VTA CoresCore Frequency213 MHzMACs per core169Memory Throughput19.2GB/s (DDR4-2400)Number precisionINT8PerformancePower EfficiencyThe DLIS power efficiency of VTA-NIC is 6.1x better than that of GPU (Nvidia V100).Tail LatencyAt high load, the tail latency of heterogeneous systems unexpectedly increases. With our chip, the tail latency is predictable since it is proportional to the load.BackgroundRecently, web applications are often built on microservices.DL Inference Serving (DLIS) is one of those microservices1.DLIS is provisioned with a special accelerator instance2.The microservices/instances are loosely coupled via APIs.BackgroundAccelerator instances risk inefficient data movement.1.Moving data via host processors decreases the accelerator's utilization.3a.In our preliminary experiments, half of the DLIS latency was caused by moving data.2.Under high-load conditions, the interference of host processors degrades DLIS tail latency by up to 100 times4.a.In the real cloud, 9% of light DLIS tasks suffer server tail latency, and half of the serving time is waiting time.5Model: ResNet-18@TensorRTPrecision: INT8System: Triton Inference ServerAccelerator: Nvidia V100

Towards the deployment of flexible 5G mobile networks, this paper presents a hierarchical coordinated radio-resource scheduling method along with a scheme for its practical hardware implementation in a field-programmable gate array (FPGA). The scheduler in the 5G era will have to quickly perform coordinated scheduling for a huge number of transmission antennas and support flexibility for advanced scheduling algorithms. To meet these requirements, we designed an FPGA-based scheduler that hierarchically controls the radio transmissions of all transmission antennas beyond a central unit. Experimental measurements reveal that the FPGA-based hierarchical coordinated scheduler shows comparable processing speed on the radio-frame time scale. Moreover, in numerical simulations, the overall system throughput with the hierarchical coordinated scheduler is 1.25 times higher than that obtained by the conventional method when the number of transmission antennas and mobile terminals are 32 and 256, respectively. Our proposed scheduling method will enable the deployment of flexible 5G mobile networks.

This paper discusses a throughput enhancement technique for a coordinated radio-resource scheduler with a hardware accelerator in low-latency 5G mobile communications systems. In these 5G systems, the scheduler will have to search for the optimal combination of antennas and mobile terminals (MTs) from a huge number of possibilities within a sub-millisecond scheduling period. Without increasing the computational resource, it would be difficult to obtain the optimal combination when the number of accommodated MTs is large. To overcome this issue, the system throughput enhancement technique dynamically controls the search space on the basis of the number of MTs. This enables the scheduler to quickly approach the optimal combination under the computational resource constraint. Simulated results revealed that the scheduler with a hardware accelerator of 15.1 Mgates can search for the optimal combination that achieves higher system throughput within a 0.2-ms scheduling period. By dynamically controlling the search space, the scheduler performs effectively regardless of the number of MTs. The new scheduler will enable a practical future low-latency 5G system.

Development of a system is complex, requiring a well-structured process to manage the range of tasks involved and their work products. There are many models and processes available for structured development, including the well-known Waterfall and Agile models. Recent standards for safety-critical system development utilise the V-model, such as the process given in the ISO 26262 standard for functional safety of road vehicles. However, the process clashes with the commonly-expressed desire for greater reuse of development artifacts in robotics. We have experimented with applying a process, the Object-Oriented Systems Engineering Method, to the design of a robotic wheelchair. This paper describes our application of the process to a safety-critical robot, as well as our use of SysML for managing design information and ZipC for code generation and verification. We discuss our experiences, both good and bad, in order to inform other robot developers of what to consider when choosing a process and tools.

This paper presents a novel PON protection configuration using N:M protection. The proposed configuration has several advantages including a flexible and scalable design and increased bandwidth per user. As a result of both cost and reliability estimation, we indicate that a self-hold type three-dimensional configuration is optimal as an optical switch used in proposed system. In addition, we conduct an experiment using a 10-Gbit/s class Ethernet PON prototype to evaluate the switching time of the system, and we clarify the importance of switching without the ONU link down for realizing rapid switching.

This paper proposes two techniques for reducing the buffer size and computational complexity of an aggregation layer-2 switch (L2SW) in access systems by using buffer observation and multilevel dynamic bandwidth allocation (DBA). The conventional architecture for providing cousin fairness, which realizes fairness among multiple passive optical network (PON) branches, needs a huge buffer in an L2SW that depends on the number of optical network units (ONUs). Our proposal reduces the required buffer size for an L2SW that depends on the number of optical subscriber units (OSUs), which is much smaller than the number of ONUs. The proposed techniques reduce by more than two thirds the amount of unfairly distributed bandwidth caused by the lack of cousin fairness. A simulation result obtained with our proposed approach shows improved cousin fairness among multiple PON branches with a smaller buffer.

Having analyzed the results of projects concluded successfully in the last several years, we have shown project management processes as quantitative data. Using those data, we have created a guideline for customizing the project management processes. We have found out effectiveness of the guideline by applying it to a couple of pilot projects. The projects applied an iterative approach. Through the success of the pilot projects, we have also discovered that the past data of a waterfall development style project can be used as analysis input for an iterative development project.

This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC).