A monolithic silicon-based electronic path integrated circuits suitable for parity-time symmetric optoelectronic oscillators (PT-symmetric OEO) in$0.25~\mu $m SiGe BiCMOS is proposed in this paper. The OEO consists of electrical and optical paths. In the electronic path, two transimpedance amplifiers (TIA) cores are employed to receive the photocurrent from photodiode (PD) in the gain loop and PD in the loss loop of the PT-symmetric OEO respectively. An active combiner synthesizes signals in the electrical domain and converts them into differential signals, simultaneously functioning as an active balun. The combined signal is processed through an active vector-sum phase shifter (VSPS) and a driving amplifier (DRV) to drive the optical phase modulator (PM). A feedforward coupling capacitor is employed to enhance the CMRR of the active balun and improve the phase control accuracy and operational bandwidth of the VSPS, which is beneficial for enhancing the side-mode suppression ratio (SMSR) of the PT-symmetric OEO. The optical path comprises a PT-symmetric mode-selection structure, which is composed of a polarization controller (PC), a polarization beam splitter (PBS), and photodetectors (PD), and a microwave photonic filter with a phase modulator (PM) and a phase-shifted fiber Bragg grating (PS-FBG). Based on the monolithic electrical path in$0.25~\mu $m SiGe BiCMOS and the optical path constructed with commercial components, a frequency-tunable PT-symmetric OEO system is implemented. The proposed electronic path IC for PT-symmetric OEO achieves a measured operating bandwidth of 2.7 -12.2GHz, a gain adjustment range of 31.0 - 57.2dB, and a phase adjustment range of 360°. The constructed OEO achieves a frequency tuning range of 4-12GHz, a phase noise of -110.4 dBc/Hz at 10kHz offset, and a SMSR of 47.3dB. To the best of the authors’ knowledge, this is the first fully-integrated electronic path IC, tailored for PT-symmetric OEO, which achieves a relative tuning range of around 100% and a side-mode rejection of 47.3dB.

This paper presents a wideband high-efficiency linear time-domain waveform-complementary distributed power amplifier (TDWC-DPA), with gain cells (GC) composed of deep Class-AB and inverse-Class-C structures. The proposed inverse-Class-C GC consists of N-type devices operating in the saturation region instead of in the cutoff region compared with conventional Class-C amplifiers. This allows the amplifier to conduct near the valleys of the input signal. This unique characteristic enables the inverse-Class-C GC to achieve an opposite conduction state compared to deep Class-AB amplifiers. Furthermore, distributed base-and collector-networks are deployed to combine deep Class-AB and inverse-Class-C GCs and form the standard sinusoidal signals with low harmonic content further through. The amplifier achieves enhanced in-phase superposition of fundamental waves with proper bias of the common base transistor. The fabricated TDWC-DPA achieves 41.8 dBc second harmonic suppression (HS) and 39.1 dBc third harmonic suppression respectively. With integrating 500 V output ESD protection, the single-ended TDWC-DPA achieves a$-$3-dB bandwidth from 2 to 14 GHz and a small signal gain of 20 dB. The maximum power-added efficiency (PAE) is 33.6%, the saturated output power is 19.4 dBm and the output 1 dB compression point (P$_{\mathrm{1dB}})$is 19.2 dBm. The proposed TDWC-DPA achieves significantly enhanced linearity with maintaining a competitive efficiency in a wide frequency range and can support communication systems deploying high-order modulation formats.

This paper presents a fast-locking 28 Gbaud PAM-4 CDR targeting for burst-mode operation. By implementing an oversampling scheme tailored for the preamble stage signal according to the pattern appearance regulation, the trade-off between the loop bandwidth and the convergence time in the conventional CDR is avoided. In addition, to reduce power consumption in the oversampling mode, a 3-phase sampling scheme equivalent to 3 times-oversampling with a minimal phase shift range of 30° is proposed. The PAM-4 burst-mode CDR also includes a conventional Bang-Bang phase locking loop with a bandwidth of 5 MHz. Realized in a 65nm bulk CMOS technology, the CDR chip achieves 28 Gbaud PAM-4 burst-mode clock recovery within 10 ns. With integrating slicers, phase interpolators and output buffers, the total power consumption of the CDR is 154 mW. Compared with the prior arts, to the best of authors’ knowledge, the proposed CDR first achieves on-chip phase-locking with PAM-4 Burst signals, based on the proposed PAM-4 burst-mode signal tailored 3-phase oversampling scheme.

A continuously tunable optoelectronic oscillator (OEO) with three frequency tuning mechanisms is proposed to enable frequency locking covering the whole working band. Three frequency-tuning mechanisms are employed simultaneously in the OEO, including a course tuning of microwave photonic filter, a fine tuning of phase shifter and a frequency calibration of direct digital synthesizer (DDS). The introduction of frequency compensation signal achieved by DDS increases the locking range of OEO so that the lock-out problem caused by mode hopping can be effectively solved. In the proof-of-concept experiment, a 3–6 GHz tunable RF oscillating signal has been successfully verified. The locking range of the proposed OEO is extended over 11 times compared to conventional OEO. With a 500 m optical fiber inserted in the loop, the phase noise is measured to be −110 dBc/Hz at 10 kHz offset. The Allan deviation is improved from$1.7\times 10 ^{-8}$to$1.6\times 10 ^{-11}$at 1000 s averaging time. To the best of the authors’ knowledge, this is the first time that a frequency tunable OEO with full locking range has been implemented.

A${V}$-band heterodyne radiometer in SiGe BiCMOS employing a capacitor-reused absorptive inter-stage matching network is firstly proposed, which prevents from employing a circulator, a resistive attenuator or two quadrature couplers in the conventional high-sensitivity cascaded receiver. This radiometer consists of a five-stage low noise amplifier (LNA) with the proposed reflectionless output matching network (RLMN), and a double-balanced Gilbert mixer stage with integrated Marchand baluns. In the RLMN, the capacitor for in-band matching is reused as an impedance inverter in the lossy absorptive network to eliminate reflections. Utilizing the reflectionless LNA, the radiometer eliminates the out-of-band reflected signals round the interfaces of LNA and mixer. Fabricated in a$0.13~\mu \text{m}$SiGe BiCMOS technology, the reflectionless LNA achieves a gain of 31.9 dB@56 GHz, an absolutely stable operation in-band and 11 times larger stability factor out-of-band than conventional LNAs. Moreover, the implemented heterodyne radiometer achieves a noise equivalent temperature difference (NETD) of 0.3 K which is even comparable with wideband direct-detection radiometers.

The concept, principle, and method of microwave radiometric imaging with mirrored aperture synthesis (MAS) were proposed by the Huazhong University of Science and Technology (HUST), Wuhan, China. MAS can achieve higher spatial resolution without extending the size of the antenna array. However, the MAS principle has not been sufficiently validated by practical experiments. To solve this problem, an innovative experiment system of MAS at the V-band (MAS-V) has been developed by HUST. Experiments on the interference fringe pattern, spatial resolution, as well as the imaging of an electric warmer and the absorbing material in the styrofoam box filled with liquid nitrogen are performed. The initial experimental results demonstrate that MAS can achieve higher spatial resolution with the same antenna array compared with the conventional AS. For MAS, the experimental results are consistent with theory and simulation results.

In this design contest, the design methodology leading to a high performance Millimeter-wave amplifier in 0.13 μm SiGe BiCMOS is elaborated. Equivalent circuit models of the utilized cascode shielding structure are developed to assist the amplifier design. Meanwhile, final layouts of the passive connections are verified by 3D electromagnetic simulation in ANSYS HFSS. The implemented amplifier obtained a gain more than 45 dB in band, which is the gain record of silicon-based amplifiers in W-band.