The increasing need for validating heterogeneous Systems on Chip (SoC) before their costly fabrication gives rise to the development of numerous virtual prototyping tools, allowing not only the modeling of such systems, but also the simulation of the environment in which they will be embedded, including the crucial software. SoC designers indeed require flexible simulation frameworks that follow a component-based approach and that cover a wide field of physical/engineering disciplines... and no questions asked about the simulation intrinsics. Furthermore, for SMEs, laboratories, and enthusiastic makers with limited funding, the cost of these frameworks makes them unaffordable, especially when the target system hardware is supposed to be Open Source too. In this paper, we detail the principles of an Open Source SystemC Multi-Disciplinary Virtual Prototyping (SystemC MDVP) framework, which directly tackles with all these issues. We introduce the key concepts and methodology (relationships between Models of Computation and overall synchronization techniques) and insist on the importance of a “correct by construction” global model elaboration that allows to generate the hierarchy of solvers that make up the final simulator. We then show that a new Model of Computation, Electrical Network, has been added to SystemC MDVP to handle components with non-linear beahviors. The paper concludes with a quick presentation of the echOpen project which aims at designing a low-cost portable echography device modeled and simulated with the presented principles.

International audience

This paper presents the past, present, and perspectives of the SystemC AMS standard as well as several commercial and academic frameworks gravitating around it that have been used to develop use cases in various cyber physical domains. After an overview of the standard, two frameworks are described: the COSIDE environment that supports the virtual prototyping of embedded HW/SW systems and its interaction with AMS circuits. Second, the SICYPHOS framework that integrates SystemC AMS into the overall system development ecosystem. By an example we give details how SystemC AMS can be coupled with other simulation tools (OpenModelica) while keeping simulation speed and accuracy high. Another example shows how SystemC AMS can be used as foundation technology to create specialized user-defined models of computation (MoC).

With the growing number of cores on chips, conventional electrical interconnects reach scalability limits, leading the way for alternatives like Radio Frequency (RF), optical and 3D. Due to the variability of applications, communication needs change over time and across regions of the chip. To address these issues, a dynamically reconfigurable Network on Chip (NoC) is proposed. It uses RF and Orthogonal Frequency Division Multiple Access (OFDMA) to create communication channels whose allocation allows dynamic reconfiguration. We describe the NoC architecture and the distributed mechanism of dynamic allocation. We study the feasibility of the NoC based on state of the art components and analyze its performances. Static analysis shows that, for point to point communications, its latency is comparable with a 256-node electrical mesh and becomes lower for wider networks. A major feature of this architecture is its broadcast capacity. The RF~NoC becomes faster with 32 nodes, achieving a x3 speedup with 1024. Under realistic traffic models, its dynamic reconfigurability provides up to x6 lower latency while ensuring fairness.

This paper introduces flexible radio techniques inside integrated circuits in order to tackle the interconnect issue for many-core chips. We propose to take benefits from OFDMA for a RF-interconnect associated to a carrier allocation policy and adaptive modulation. A 20 GHz bandwidth is shared between 32 tile sets made of 32 tiles of 4 cores each, for a 4096 cores chip. We adopt a cognitive radio approach in order to dynamically share 1024 carriers, which avoids inter-cluster communication contention and decreases latency compared to conventional static approaches.

The design of wireless embedded systems needs their efficient and realistic simulation to verify that requirements are met. The reproduction of communication behavior is crucial to assess the performance of hardware and software components, e.g., dependability and energy consumption. This work presents and discusses different levels of abstraction for the simulation of the communication behavior. Each level addresses different aspects of the communication and allows to specify different kinds of detail; furthermore, it requires a specific modeling approach. Their use and the corresponding computational overhead is shown in the specific case of the Bluetooth standard. We also show that simulation results obtained at a low abstraction level can be used at a higher one to drive design choices.

Synthetic biology is an emerging field at the interface between biotechnology and engineering sciences. It aims at designing new biological functions by assembling elementary parts (DNA sequences) based on design approaches inspired from those used for the design of complex microsystems. The development of efficient tools to support the design is therefore a technological bottleneck that could prevent the development of this technology. This issue is tackled in this paper by reusing as much as possible the existing design flow of heterogeneous microsystems. Focus is put on modeling and simulation tasks for which biology differs from standard physical domains by different aspects. In this paper, some methods that have been implemented to address these issues are discussed. The main shortcoming is that they lead to models that are far more complex than their electronics counterparts. As a consequence, simulation time becomes a big challenge in design processes. A solution suggested in the last section consists in simulating these models on Graphics Processing Unit, with a x40 speed up.

A paradigm shift is apparent in Chip Multiprocessor (CMP) design, as the new performance bottleneck is becoming communication rather than computation. It is widely provisioned that number of cores on a single chip will reach thousands in a decade. Thus, new high rate interconnects such as optical or RF have been proposed by various researchers. However, these interconnect structures fail to provide essential requirements of heterogeneous on-chip traffic; bandwidth reconfigurability and broadcast support with a low complex design. In this paper we investigate the feasibility of a new Orthogonal Frequency Division Multiple Access (OFDMA) RF interconnect for the first time to the best of our knowledge. In addition we provide a novel dynamic bandwidth arbitration and modulation order selection policy, that is designed regarding the bimodal on-chip packets. The proposed approach decreases the average latency up to 3.5 times compared to conventional static approach.

This paper addresses the important issue of fault tolerance in network-on-chip (NoC) and presents an on-the-field test and configuration infrastructure for a 2-D-mesh NoC, which can be used in many generic shared-memory many-core tiled architectures and MPSoCs. This paper also details all the hardware and software means needed to: 1) initialize the NoC in a clean state (self-deactivation of faulty NoC components using a controlled built-in self-test strategy) and 2) set up a distributed collaborative configuration infrastructure that can be used to make the chip autonomously determine, during its initialization, the operational degraded architecture, identify and bypass black holes. Experimental results prove that the approach is effective and lightweight in terms of additional software and hardware resources.

The paper presents the principles, techniques and tools for the efficient modeling and simulation, at the component level, of an heterogeneous system composed of Wireless Sensor Network nodes that exhibits complex multi-discipline feedback loops that are likely to be found in many state-of-the-art applications such as cyber-physical systems. A Precollision Mitigation Braking System (PMBS) is used as a pragmatic case study to validate the whole approach. The component models presented (60 GHz communication channel, QPSK RF transceiver, CMOS video sensor, digital microcontroller, simplified car kinetic engine) are written in SystemC and its analog Mixed-Signal extensions, SystemC-AMS, and belong to five distinct yet highly interwoven disciplines: newtonian mechanics, op to-electronics, analog RF, digital and embedded software. The paper clearly exhibits the complex multi-discipline feed- back loop of this automotive application and the related model composability issues. Using the opto-electrical stimulus and the received RF inter-vehicle data, a car is able to exploit its environmental data to autonomously adjust its own velocity. This adjustment impacts the physical environment that in turns modifies the RF communication conditions. Results show that this holistic first-order virtual prototype can be advantageously used to jointly develop the final embedded software and to refine any of its hardware component part.

In this paper, we present a software approach for localization of faulty components in a 2D-mesh Network-on-Chip, targeting fault tolerance in a shared memory MP2SoC architecture. We use a pre-existing and distributed hardware infrastructure supporting self-test and de-activation of the faulty components (routers and communication channels), that are transformed into “black hole”. We detail the software method used to localize these “black holes”, and centralize the information in a single point, where a modified global routing function can be defined. This embedded software makes an extensive use of a distributed fault-tolerant configuration firmware assisted by a Distributed Cooperative Configuration Infrastructure (DCCI), that is also presented. Finally, “black hole” detection and localization coverage is evaluated.

The simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs). The SystemC TLM2.0 (Transaction Level Modeling) approach accelerates the simulation by using Interface Method Calls (IMC) to implement the communications between hardware components. Another source of speedup can be exploited by parallel simulation. Multi-core workstations are becoming the mainstream, and SMP workstations will soon contain several tens of cores. The standard SystemC simulation engine uses a centralized scheduler, that is clearly the bottleneck for a parallel simulation. This paper has two main contributions. The first is a general modeling strategy for shared memory MPSoCs, called TLM-DT (Transaction Level Modeling with Distributed Time). The second is a truly parallel simulation engine, called SystemC-SMP. First experimental results on a 40 processor MPSoC virtual prototype running on a dual-core workstation demonstrate a 1.8 speedup, versus a sequential simulation.

This paper describes the design principles of a software based on-line testing application used to monitor manycore architectures running multi thread functional applications. The key idea is to have a non intrusive monitoring application running in parallel with the functional one. The monitoring application aims at detecting and reacting to software or hardware malfunctions, and can be seen as a service provided by the operating system. This monitoring method relies on the use of embedded sensors that capture physical values (temperature, ...) from the chip, or software-related indicators like CPU load. A case-study implementing this methodology has been performed and results in terms of memory usage and performance overhead are given.

The paper presents an innovative approach for the modeling and simulation of heterogeneous biological systems based on SystemC-AMS, an open-source C++ extension to the OSCI SystemC Standard. After some basic notions on synthetic biology, an analogy is drawn between this active field of research and nanoelectronics. The paper then presents the SystemC-AMS Timed DataFlow (TDF) modeling formalism used to model these multidomain devices. It also details the presented case study, a bio-compatible system with feedback consisting of a biological sensor instanciating a T flip-flop BioBrick and a EnFET, a voluntarily simple digital processing unit and an actuator based on the Hodgkin-Huxley neuron model. Some simulation results are given that validate the use of SystemC-AMS as an attractive, open-source and flexible framework for modeling complex bio-compatible systems.

The paper presents a system-level approach for the modeling and simulation of a paradigmatic wireless sensor network composed of two nodes using SystemC-AMS, an open-source C++ extension to the OSCI SystemC standard dedicated to the description of heterogeneous systems containing digital, analog, RF hardware IPs as well as embedded software. The paper is composed of three parts. The first part details the modeled WSN (physical sensor, sigma-delta ADC, ATMEGA128 8- bit microcontroller running the embedded application, QPSK-based 2.4 GHz RF transceiver), presents the corresponding implementation in SystemC-AMS, and gives an insight on how multi-frequency simulation is handled in SystemC-AMS. The second part shows how to introduce several RF designer specifications (noise figure, IIP3, ...) into models and how to express them in SystemC-AMS. The third part proves that the combination of C++ and RF baseband equivalent dramatically reduces simulation time while keeping excellent accuracy and code readability. The paper concludes on the possibilities offered by this approach in terms of validation and optimization of heteregeneous systems through open-source simulation.

The paper presents an innovative simulation scheme to speed-up simulations of multi-clusters multi-processors SoCs at the TLM/T (transaction level model with time) abstraction level. The hardware components of the SoC architecture are written in standard SystemC. The goal is to describe the dynamic behavior of a given software application running on a given hardware architecture (including the dynamic contention in the interconnect and the cache effects), in order to provide the system designer with the same reliable timing information as a cycle accurate simulation, with a simulation speed similar to a TLM simulation. The key idea is to apply parallel discrete event simulation (PDES) techniques to a collection of communicating SystemC SC-THREAD. Experimental results show a simulation speedup of a factor up to 50 versus a BCA simulation (bus cycle accurate), for a timing error lower than 10-3

This paper focuses on commonalities and differences between the two mixed-signal hardware description languages, VHDL-AMS and Verilog-AMS, in the case of modeling heterogeneous or multidiscipline systems. The paper has two objectives. The first one is modeling the structure and the behavior of an airbag system using both the VHDL-AMS and the Verilog-AMS languages. Such a system encompasses several time abstractions (i.e., discrete-time and continuous-time), several disciplines, or energy domains (i.e., electrical, thermal, optical, mechanical, and chemical), and several continuous-time description formalisms (i.e., conservative-law and signal-flow descriptions). The second objective is to discuss the results of the proposed modeling process in terms of the descriptive capabilities of the VHDL-AMS and Verilog-AMS languages and of the generated simulation results. The tools used are the Advance-MS from Mentor Graphics for VHDL-AMS and the AMS Simulator from Cadence Design Systems for Verilog-AMS. This paper shows that both languages offer effective means to describe and simulate multidiscipline systems, though using different descriptive approaches. It also highlights current tool limitations, since full language definitions are not yet supported.

This paper presents STEPS, an innovative software-based approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator applying vectors to the SoC test pins but rather as a target, a huge repository of 32-bits test data and control commands. The ATE is connected to the functional SoC external RAM controller interface. The only additional test component in the SoC is a P1500 test processor that converts test data into serial P1500 streams. This paper applies the STEPS methodology to SoCs containing a VCI-compliant interconnect, a microprocessor, P1500-compliant IP cores and an external RAM controller interface. Using the ITC02 SoC benchmarks, a comparison is done between the STEPS architecture and a classical bus-based strategy.