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Ron J. Gal-Ezer

dblp:19/3875 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1982
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 56% Parallel and multicore computing · 36% Processor architecture and microarchitecture · 8%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing
parallel programming models
0.011982
Wavefront Array Processor: Language, Architecture, and Applications · IEEE Trans. Computers 1982
Hardware accelerators and domain-specific architectures
systolic array
0.011982
Wavefront Array Processor: Language, Architecture, and Applications · IEEE Trans. Computers 1982
Hardware accelerators and domain-specific architectures › systolic array
wavefront array processor
0.011982
Wavefront Array Processor: Language, Architecture, and Applications · IEEE Trans. Computers 1982
Processor architecture and microarchitecture › dataflow architecture
dataflow machine
0.011982
Wavefront Array Processor: Language, Architecture, and Applications · IEEE Trans. Computers 1982
Parallel and multicore computing
parallel architecture
0.011982
Wavefront Array Processor: Language, Architecture, and Applications · IEEE Trans. Computers 1982

Methods — techniques the papers use, named apart from their topics

computational wavefront · 0.0MDFL · 0.0
YearPublicationVenuePosition
1982 Wavefront Array Processor: Language, Architecture, and Applications
abstract
This paper describes the development of a wavefront-based language and architecture for a programmable special-purpose multiprocessor array. Based on the notion of computational wavefront, the hardware of the processor array is designed to provide a computing medium that preserves the key properties of the wavefront. In conjunction, a wavefront language (MDFL) is introduced that drastically reduces the complexity of the description of parallel algorithms and simulates the wavefront propagation across the computing network. Together, the hardware and the language lead to a programmable wavefront array processor (WAP). The WAP blends the advantages of the dedicated systolic array and the general-purpose data-flow machine, and provides a powerful tool for the high-speed execution of a large class of matrix operations and related algorithms which have widespread applications.
Sun-Yuan Kung, K. S. Arun, Ron J. Gal-Ezer, D. V. Bhaskar Rao
IEEE Trans. Computers3