The paper proposes a two-step scan cell partitioning scheme to identify the error-capturing scan cells in a scan-BIST environment. In the first step, a deterministic partitioning scheme is used, whose target is to maximize the correlations between different scan cells in fault diagnosis since different scan cells have very different probabilities of capturing fault effects. In the second step, a previously proposed random partitioning scheme is used to generate additional partitions. Experimental results are reported on the five largest ISCAS'89 benchmark circuits and compared with that for the random partitioning scheme and another earlier work using interval-based partitioning scheme.

This paper describes a circuit independent weighted pseudo random BIST pattern generator based on bit-flipping. The circuit dependent data is stored in memories so that different circuits can use the same BIST structure by only changing the data in the memories. New approaches are proposed for compressing and storing the bit-flipping data. Experimental results show that the proposed method reduces the size of the memory considerably while using similar test lengths as a recent method based on bit-fixing.

Detecting single stuck-at faults more than once has been shown to be an effective way to achieve high defect coverage. Recently it was observed that the number of tests required to achieve n-detection of single-stuck-at faults using pseudo-random sources may increase as n.logn with increasing values of n. In this paper, we investigate weighted pseudo-random BIST for n-detection of single stuck-at faults. We propose a hardware efficient weighted pseudo-random test pattern generator. Experimental results show that the proposed test pattern generator achieves n-detection of single stuck-at faults with test set sizes growing linearly with n. The hardware overhead grows modestly with n.

Recently, Markov sources were shown to be effective in designing pseudo-random test pattern generators with low area overhead for built-in self-test of scan designs. This paper presents a new test pattern generation scheme based on a Markov source and a partial bit-fixing technique. A new method is proposed for the computation of the state transition probabilities of the Markov source based on the statistics of a deterministic test set. This is enhanced by partial bit-fixing logic, which fixes a group of consecutive inputs to all-0 or all-1. Experimental results show that the proposed BIST scheme can achieve 100% fault coverage for large benchmark circuits with reduced hardware overhead and reduced pattern counts compared to the earlier method using Markov sources.

Recently, Markov sources were shown to achieve 100% fault efficiency at low area overhead when used as pseudo-random pattern generators in scan BIST. In this paper we give a new method of designing Markov sources. The new design attempts to match probabilities of 1 to 0 and 0 to 1 transitions in consecutive bits of a set of test vectors, taking into account that the transition probabilities may be different for different bit positions. Experimental results show that the proposed method considerably reduces the hardware overhead and test lengths required to achieve 100% fault coverage.