Analog compute-in-memory (ACIM) architectures emerged as energy efficient matrix–vector multiplication accelerators utilized for neural network inference in power-constrained environments. However, the security implications of ACIM hard-ware remain almost entirely unexplored. In particular, no previous work has evaluated information leakage of fabricated ACIM hardware through power side-channels. This work presents the first measured power side-channel analysis of a fabricated 28 nm ACIM macro. Using a convolutional neural network (CNN) work-load, we show that power traces exhibit strong data-dependent information leakage that allows accurate reconstruction of private input images, with a mean structural similarity index measure (MSSIM) of up to 0.71.

This paper presents the design of a wideband pipelined multi-stage noise shaping (MASH) continuous time (CT) delta-sigma modulator (DSM). The quantization error of the overall$1^{\mathrm {st}}$-stage DSM is extracted as the input of the$2^{\mathrm {nd}}$stage, while the outputs of both stages are simply combined without using any digital filters. Overall, different shaping functions are generated for both QN without requiring any digital QN cancellation. Therefore, the pipelined MASH (PMASH) significantly mitigates QN leakage while retaining the decent loop stability of a traditional MASH. Additionally, several analyses have been made for the PMASH topology, e.g. the design guideline, the signal transfer function (STF), the robustness, etc. Clocked at 800MHz and enabling on-chip DAC calibration, the 65nm CMOS prototype with an exemplary 2-2 topology using multi-bit quantizers achieves 82.6 dB SNDR, 98.8 dB SFDR over 15.4 MHz BW at −0.5 dBFS 1.8 MHz input. The power consumption is 16.9 mW with 1.2V/1.5V supplies. It results in a competitive FoM${}_{\mathrm {S\vert SNDR}}$of 172.2 dB, while it avoids any off-chip calibrations.

Tri-level current-steering digital-to-analog converters (DACs) offer an appealing balance between resolution and static linearity, making them attractive to be employed as feedback DAC in high-resolution continuous-time Delta-Sigma-Modulator (CTDSM). However, they are susceptible to non-linearity caused by dynamic, signal-dependent switching errors degrading the overall performance. While such errors have been thoroughly analyzed in literature for single-bit current-steering DACs, they have not been thoroughly investigated for tri-level current-steering DACs. As a result, this paper investigates the sources of these errors and demonstrates their severity by analysis and simulations employing a tri-level DAC in an exemplary CTDSM. In addition, techniques for mitigating dynamic errors, including device sizing and switching schemes, are discussed to help mitigate the non-linearity.

As AI and its applications evolve, efficient hardware is required to run the novel algorithms. Compute platforms with a high degree of parallelism, such as matrix-vector multipliers, meet the need to process large homogeneous loads of operations. However, most of the matrix-vector multiplications required by the AI algorithms are larger than what the actual hardware supports. The operations must therefore be tiled into blocks that fit on the given hardware. Finally, the partial sums generated by the hardware for each tile must be accumulated or concatenated into the complete result. Especially with mixed-signal compute-in-memory architectures, this can lead to quantization on two levels. First, an ADC quantizes the partial sums generated for each tile. Then, the algorithm performs another quantization of the final result to limit bitwidth and resource consumption in adjacent computations. While quantizing only the partial sums or only the final results has been studied extensively, the combination of the two has yet to be investigated. This work introduces a simulator to understand the effects of quantization caused by multiple quantization steps on different levels. It is based on a generic, stochastic representation of value probabilities using histograms. Common operations such as scaling, rounding, and accumulation are implemented in this representation, allowing the effect of quantization to be studied in a matrix-vector-multiplier application. It is shown, that the selection of tilesize, ADC bitwidth and clipping technique form a complex trade-off, which can be solved using PSumSim. PSumSim is available under https://github.com/Joschua-Conrad/PSumSim.

The design of ultra-low power, highly linear and low noise Delta-Sigma modulators (DSMs) is an active topic in research and industrial application to realize high-resolution analog-to-digital converters (ADCs) for applications such as audio, sensor or IoT digitization. In such DSMs, the first integrator stage usually consumes most of the power, which is why innovative amplifier architectures have been proposed. This paper presents a case study of different state of the art power-efficient operational amplifier (OpAmp) topologies in a 180 nm CMOS technology using a standard 1.8V supply. A detailed comparison is made in terms of power, noise, area, linearity, and design effort, which can serve as a guide for designers when choosing the most suitable amplifier architecture for such application.

The theory of incremental Delta-Sigma (I-DS) converters relies on memoryless operation between consecutive Nyquist samples. This is achieved by resetting the analog loop-filter and digital reconstruction filter every Nyquist period. It is shown that the use of reconstruction filters with negligible first-sample weights opens the possibility of removing the periodic reset from the analog loop filter of incremental Delta-Sigma modulator (I-DSM) while maintaining memoryless operation. The periodic reset can further be removed from reconstruction filters whose impulse response is inherently finite. Combining the two features enables free-running Delta-Sigma (DS) converters to be used in time-domain multiplexing applications and without inter-channel interference.

Continuous-time (CT) Delta-Sigma (DS) ADCs are a popular choice for high resolution, medium bandwidth applications. A critical challenge is the excess-loop-delay (ELD) in the feedback path of the modulator, which causes performance degradation and instability. For free-running Delta-Sigma modulators (DSMs), performance can be fully recovered by adjusting the loop filter to restore the original noise transfer function (NTF) without ELD. For CT incremental Delta-Sigma (I-DS) ADCs, this has not been specifically investigated, but it is worth noting that the process of ELD compensation is slightly different. In this paper, we investigate the effect of ELD on I-DS ADCs and show that the performance cannot be fully recovered by NTF engineering as in the free-running case, but requires signal transfer function (STF) engineering as well. We also present solutions on how to engineer the STF and how to fully recover the performance even in the presence of ELD in CT I-DS ADCs.

The maximum stable amplitude (MSA) is an important characteristic of a Delta-Sigma modulator (DSM) for high resolution and power efficiency. In free-running DSMs it is known that the MSA usually corresponds to a similar value as the amplitude with the maximum signal-to-quantization-noise ratio (SQNR) and that it depends on several factors including: loopfilter architecture, loopfilter scaling and aggressiveness, internal quantizer bit-width, signal transfer function (STF) and input frequency. Commonly, incremental Delta-Sigma (I-DS) analog-to-digital converters (ADCs) are derived from free-running prototypes enhanced by a periodic reset, and the assumption is that the underlying characteristics remain the same. In contrast, we elaborate in this work that the MSA of I-DS ADCs doesn’t correspond to the amplitude with the maximum SQNR anymore and that this amplitude is not exclusively determined by the DSM, but also depends on the chosen reconstruction filter. Furthermore, the reasons for this interdependency of the reconstruction filter and the amplitude with maximum SQNR are highlighted and solutions to solve this problem are presented.

This article presents a wireless neuromodulation headstage prototype intended for in-vitro recording and stimulation in freely behaving mice. The prototype allows independent stimulation on 32 channels and can record up to 32channels in the local field potential (LFP) band, while the simultaneous recording in the action potential (AP) band is limited to 3 channels when data is not compressed. All recorded data is directly streamed via Bluetooth Low Energy (BLE), enabling immediate analysis during the experiment. The small size of 20x24 x8 mm and a low total weight of 3.9g makes this neurologger suitable to be used on small rodents such as mice. A moderate power consumption of 29.3mW for 32channel recording and transmission of LFP band data ensures a long uninterrupted operation of almost 5hours.

Continuous-time (CT) Delta-Sigma-Modulators (DSMs) are widely utilized in systems requiring wide bandwidth and high resolution. While opamp-based RC integrators are favoured for their excellent linearity, they introduce low-input impedance and complicate the ADC driver. On the other side, Gm-C integrators provide high input impedance, making them more power-efficient, but they suffer from non-linearity, thereby limiting the input range. This paper explores the limitations of a specific non-linearity cancellation technique applied in DSM system-level. The principles of this technique are reviewed, and the challenges of using it at low oversampling ratio (OSR) are investigated. A theoretical analysis is presented, matching with simulation results.

Multibit (MB) quantization allows high resolution Delta-Sigma modulators (DSMs) with low oversampling ratio (OSR). Furthermore, it allows higher maximum stable amplitude (MSA), achieves reduced jitter sensitivity, and relaxes the dynamic requirements on the DSM loop-filter (LF). However, MB quantization adds a dominant source of non-linearity due to element mismatch in the MB digital-to-analog converter (DAC) which often dominates the performance. State of the art (SoA) presents many calibration techniques, though digital power and area consumption can be high and calibration time be significant. In this paper we target a calibration-free DAC based on dual quantization and propose to employ a Multistage noise SHaping (MASH) Digital-DSM (DDSM) to avoid architectural compromises between the main DSM LF and the DDSM DAC. The implementation trade-offs are illustrated, and stability constraints in both the main LF and the DDSM are addressed. An exemplary implementation is derived and simulated, and the results shall lay the foundation for future circuit implementations of MASH DDSM to realize MB DSM with intrinsically high linearity.

Dedicated neural-network inference-processors improve latency and power of the computing devices. They use custom memory hierarchies that take into account the flow of operators present in neural networks and convolutional layers. For efficient implementation, such network topologies can greatly benefit from hardware-cost optimization using automated network-architecture search. Thereby, cost functions predict the suitability of a network topology for a given type of inference hardware. A differentiable neural-architecture search that optimizes both weights and topology in a single training requires cost models to be differentiable in the dimensions of weight and activation matrices. State-of-the-art differentiable cost models require time-consuming system-level measurements or simulation results, or do not encounter the hardware structure at all. This work presents a simple yet effective procedure for deriving a differentiable neural-network-accelerator cost-model that is suitable for any type of accelerator. It is based on hardware-independent parameterization and a novel differentiable divide-ceil function, as well as hardware-specific modeling. The resulting differentiable model can be reconfigured to the actual hardware size and memory structure to predict the inference energy for an exact network topology. The modeling and prediction are demonstrated for a state-of-the-art SRAM-based inference-accelerator and for the Eyeriss accelerator, inferring different state-of-the-art neural networks, resulting in excellent agreement with measured hardware.

Active RC-Integrators are one of the main building blocks of continuous-time Delta-Sigma-Modulators (CTDSMs). The DC gain and gain-bandwidth product (GBW) of their Operational Ampifiers (OAs) play an important role in the modulator stability and performance in terms of signal-to-quantization-noise ratio (SQNR) as well as spurious-free dynamic range (SFDR). Negative-R assisted integrators have been introduced to reduce the CTDSMs sensitivity to OA non-idealities, where the negative-R has shown linearity improvements in low-power CTDSMs for relatively narrow bandwidth applications. However, the negative-R concept has not been widely applied for wideband applications. Wide-band CTDSMs in particular are more sensitive to the non-idealities of the OA GBW and especially in the associated phase-shift compared to their narrow-band counterparts. This paper provides insight into the effect of negative-R assistance on the GBW of the OA, where it is shown, that the phase-shift of the integrator due to finite GBW is not reduced by the negative-R assistance, and still remains an issue to be considered in the design of a wide-band CTDSMs.

This work links Ring Oscillator (RO)-Physical Unclonable Function (PUF) specific design parameters with previously neglected area consumption per PUF bit. In prior art, the PUF specific design parameters such as number of ROs in a given RO collection that can be compared to one another and readout time are optimised in terms of e.g stability and/or power consumption. The influence of these design parameters on the effectively required area per bit remains overlooked, since optimization on area is mostly done simply by designing small ROs. This work establishes a relationship between the general design parameters and the area per bit for RO-PUFs. Using finite frequency readout resolution by means of a limited readout time, the RO-PUF is transformed into graph-theory and by finding a Minimum Spanning Tree (MST), the best possible yield of a given collection of ROs is determined. The given collection together with variable yield is then mapped to a certain demand on area per bit. An extensive yield analysis is performed which then is again mapped to a certain area per bit, leading to the proposed connection between readout time, amount of ROs in a collection and area per bit.The system-level analysis performed shows that a set of 8 ROs represents a sweet-spot in terms of area per bit as well as low read-out time.

Element mismatch error shaping had been thoroughly studied in free-running Delta-Sigma (DS) ADCs, which enabled using multi-bit quantizer in the loopfilter while shaping the non-linearity errors of the feedback DAC unit element mismatch. A popular shaping technique in free-running DS ADCs is the simple rotational data-weighted averaging (DWA), which was shown to be ineffective in state of the art (SoA) higher order incremental Delta-Sigma (I-DS) ADCs. Hence, prior SoA proposed smart shaping techniques tailored for I-DS ADCs, though adding significant area and power complexity compared to DWA. In this work it is shown that by applying periodic reset to the DWA’s rotation index renders it very feasible and effective for DAC mismatch shaping even in higher order I-DS ADCs without the need of changed algorithms.

The offset cancellation in incremental Delta-Sigma (IDS) ADCs has to be treated differently compared to the cancellation in their freerunning counterparts. In the state of the art (SoA), there exists a lack of theory about this topic. Therefore, in this paper offset propagation and cancellation in I-DS ADCs is analysed. Thereby the idea of fractal sequences to cancel the offset is revised and extended to a more general description to cancel the offset at the output of the I-DS ADC. The derived theory is further explained and backed up by simulations for an exemplary modulator architecture. The intention is to give a deeper understanding on the offset propagation and cancellation in I-DS ADCs and close this gap in the SoA.

This paper introduces an Artificial Neural Network (ANN) to predict the stability of Delta-Sigma modulators (DSMs) and, furthermore, shows its beneficial employment in a genetic optimization algorithm. Since a DSM is a non-linear system, its stability often can’t be predicted by simple algebra. Therefore, a new approach predicting the stability of DSMs using an ANN is presented in this work. It is shown how the data generation and training of such a network can be done. Furthermore, the derivation of high-level coefficients for DSMs is a tedious task, which is often solved by time consuming simulations. The application of the derived ANN in a genetic algorithm to find these high-level coefficients leads to the significant time savings of close to 50%.

A background bond wire defect detection method for high accuracy differential DC-current read-out applications is presented. It is demonstrated how it overcomes the SoA limitations and allows to concurrently detect bond wire defects, such as bond opens, shorts to ground/Vsupplyand shorts between the connections, without interfering with the main functionality of a sensor readout circuit. A comparison of existing solutions is carried out concerning error coverage as well as the disturbance of the functional measurement signal. Functionalities and limitations are separately discussed and the need for the proposed method is derived from self-induced offset problems. Finally, a closed loop solution is presented that avoids the creation of offsets by impedance mismatches. Matlab Simulink is then used to simulate the techniques in an exemplary system and to compare the results.

This work presents a 600MS/s 10-bit single-channel asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) using a highly linear unit via-based delta-length capacitive digital-to-analog converter (C-DAC). The plain and regular segmented C-DAC structure is presented in detail, which provides close to 13-bit static matching with an area of only 1160 μm2. A Flash ADC is employed to pre-load some MSBs for improved conversion speed while also efficiently utilizing DAC segmentation, which is practically necessary in delta-length-based C-DACs. This ADC architecture can easily be extended to a time-interleaved SAR to fully take advantage of the fast Flash conversion. The ADC was fabricated in a 22nm FDSOI technology and achieves a SNDR of 51.37dB at 600MS/s with near Nyquist input while consuming 3.04mW from a 0.85V supply, which leads to a Walden FoM of 16.74fJ/conversion-step.

Transimpedance amplifiers (TIAs) are used in a wide variety of low noise current sensing frontends. A recently proposed mixed-signal TIA (MS-TIA) is an extension of the integrator-differentiator TIA but including digitization and digital differentiation. However, the MS-TIA requires a high resolution analog-to-digital converter (ADC) in order to maintain good sensitivity. Capacitive digital-to-analog converter (C-DAC) based successive approximation register (SAR) ADCs achieve high resolution at medium bandwidth with good power efficiency, however require a power hungry ADC input driver. In this paper, a combination of the MS-TIA and a modified C-DAC reset scheme is presented, which eliminates the need for a high performance ADC input driver, resulting in major improvements regarding power consumption and linearity. The results are verified by transistor level simulations in a standard 180nm CMOS technology.

The project VE-FIDES will contribute with a solution based on an innovative multi-level fingerprinting approach to secure electronics supply chains against the threats of malicious modification, piracy, and counterfeiting. Hardware-fingerprints are derived from minuscule, unavoidable process variations using the technology of Physical Unclonable Functions (PUFs). The derived fingerprints are processed to a system fingerprint enabling unique identification, not only of single components but also on PCB level. With the proposed concept, we show how the system fingerprint can enhance the trustworthiness of the overall system. For this purpose, the complete system including tiny sensors, a Secure Element and its interface to the application is considered in VE-FIDES. New insights into methodologies to derive component and system fingerprints are gained. These techniques for the verification of system integrity are complemented by methods for preventing reverse engineering. Two application scenarios are in the focus of VE-FIDES: Industrial control systems and an automotive use case are considered, giving insights to a wide spectrum of requirements for products built from components provided by international supply chains.

In this paper, the linear-exponential incremental Delta-Sigma (I-DS) ADC is analyzed as a dynamic reconfiguration technique. The influence of the parameters of the exponential phase on the performance of the ADC will be analysed and further investigated under the presence of coefficient mismatch. Furthermore, higher order linear-exponential I-DS ADCs will be introduced and the analysis is extended from first to higher order modulators, giving valuable insights and showing the benefits and drawbacks of higher order linear-exponential I-DS ADCs compared to first order ones. The intention is to give an insight and understanding of the performance improvements, limiting factors and trade-offs achieved by the exponential phase.

Recently, there is an increased demand for high-linearity applications, where the requirements on the base-band Analog-to-Digital Converter (ADC) Spurious Free Dynamic Range (SFDR) represents a challenge. Most ADC architectures suffer from element mismatch which limits the linearity, and require significant calibration, whose resolution is ultimately limiting the performance. The exception is the single-bit Delta-Sigma Modulator (DSM), where the internal Digital-to-Analog Converter (DAC) is intrinsically linear and ideally no calibration is required, making it the architecture of choice in recent high linearity implementations [1]–[3]. However, when the Over Sampling Ratio (OSR) is constrained to low values, the modulator linearity becomes intrinsically limited by the quantized operation of the modulator, even with perfectly linear DAC and ideal components in the loop filter. In this article we focus on this limitation of linearity by the quantizer, discuss how to best model it, and evaluate what are the key elements the designers have to master in order to design for best linearity.

This paper presents a power and area efficient digital communication interface for tiny distributed direct digitizing neural recorder ASICs on an ultra-flexible neural implant in a bus-like structure in order to realize a NeuroBus. The digital interface only requires 3 pins, does not need any preprogramming or trimming for address allocation and achieves a very low core area. The digital interface was implemented in a 1.2V 180nm CMOS technology and supports up to 100 spatially distributed neural recorder ASICs, consuming only$9\ \mu\mathrm{W}$of power per channel on a tiny area of$2380\ \mu\mathrm{m}^{2}$.

In this paper, analysis of linear time-variant systems is applied to incremental Delta-Sigma (I-DS) ADCs with periodic architectural reconfiguration in the frequency domain. The analysis will then be applied to the example of linear-exponential I-DS ADCs as a state-of-the-art dynamic reconfiguration technique. It is shown how a matched reconstruction filter of the reconfigured linear-exponential incremental Delta-Sigma modulator (I-DSM) can be mathematically derived. Using the calculated overall transfer functions of the linear-exponential I-DS ADC, accurate performance predictions can be given. The proposed method allows the accurate prediction of performances and gives insight and understanding of the performance improvements and trade-offs achieved by reconfiguration techniques in I-DS ADCs in general and the exponential phase in particular.

As wideband Delta-Sigma-Modulators (DSMs) are restricted in oversampling ratio (OSR), and low OSR reduces the benefit of higher order loop filters, the increase of the internal resolution is an obvious way to achieve high signal-to-quantization-noise ratio (SQNR). State-of-the-art implementations restrict the internal resolution to mostly 4-6 bits, as efficient QTZs with higher resolution add excessive delay into the DSM. Multi-step or time-interleaved-quantizer (TI-QTZs) are an effective way to enhance resolution at high sampling rate, but the resulting latency in excess of one clock cycle usually prohibits their usage in DSMs. This paper proposes a new architecture to employ high resolution multi-step QTZs, such as TI SAR or pipeline ADCs. In the proposed architecture, an excess loop delay (ELD) of several clock cycles in the LSBs is purposefully allowed. While the MSBs are conventionally ELD-compensated, the LSBs are not. The resulting error is corrected in the digital domain. It is shown that matching requirements are relaxed by first-order shaping. The idea is also applicable to a Leslie-Singh and noise-coupling architecture, which are compared to the proposed architecture in an extensive system-level analysis and simulation. Depending on the target application, an advantageous design recommendation can be given based on the presented results depending on OSR, internal bitwidth and expected analog-digital matching.

Stimulation waveforms and artifacts can exceed the neural signal of interest by several orders of magnitude, thus requiring blanking switches to avoid saturation of the front-end and extensive subsequent recorder blind-time during the recovery. Several recent publications propose to instead utilize recording front-ends with high dynamic range, however typically at the cost of reduced first-stage gain and an adversely affected noise efficiency factor. Recently, we have demonstrated a combination of blanking switches and a tuning mechanism for the pseudo-resistor based high-pass corner frequency in a recorder to achieve rapid artifact recovery by temporarily increased settling speed. In this article, we extent this by an in-depth analysis and significantly improve the artifact recovery abilities by utilizing a combination of passive electrode discharge and recorder reset, thereby improving the recovery time after stimulation significantly, to less than 10in spike recordings with maximum gain setting of 70. The measurements are conducted with a new hardware platform, and extensive in-vitro verification is provided to demonstrate the feasibility of the combined artifact recovery.

In this paper the heuristic-search based design of Sigma-Delta modulators with FIR feedback is described. Using single-bit quantizers in Sigma-Delta modulators (SDMs) is very common due to their inherent linearity. However, their binary feedback increases the requirements for the integrators and the jitter sensitivity in the loop compared to multi-bit feedback. FIR feedback tries to resolve these problems, however, requires a second compensating FIR filter and an adjusted loopfilter scaling in order to restore the original noise transfer characteristic. This not only makes the design process more challenging but also leads to increased peaking of the STF, undesirable for many applications. Therefore, in this work a heuristic-search based design approach is presented which offloads work from the designer to an automated design environment. It allows to design CT SDMs directly in the CT domain including the compensation of nonidealities and STF engineering in order to counteract the peaking. The theoretical background is described as well as the additions to the underlying design framework. Alongside, design examples are given to illustrate the advantages of this approach.

This paper presents a modified Look-Up-Table (LUT) based DAC foreground calibration for multi-bit continuous-time Delta-Sigma Modulators. The feedback DAC in DSMs is usually a performance bottleneck, as all of its errors directly add at the input node. Fore - or background error correction based on LUT can efficiently eliminate the DAC errors, but can also impose significant circuit overhead in the digital and analog domain. The presented method reduces the correction complexity while maintaining the same performance as current state-of-the-art solutions towards static and dynamic errors.

Excess loop delay (ELD) in high speed continuoustime (CT) Delta-Sigma-Modulators (DSMs) imposes design challenges and limits the use of high resolution, e.g. successiveapproximation-register (SAR) based internal quantizers, as usual compensation techniques like the use of a direct path around the quantizer come with increased swings and reduced maximum stable amplitude (MSA). In this paper, two bitwise ELD compensation approaches applicable to cascade-of-integrators with distributed feedback (CIFB) loop filters are proposed, which alleviate this problem for SAR and other multi-step quantizers by sequentially feeding bits into the feedback loop when they are available (MSB first, LSB last). Loop-filter equivalence for such bitwise ELD compensation is analytically derived. System-level simulations using Matlab & Simulink for exemplary 4-bit 2nd, 3rd and 4th-order modulators show 40% reduction of the last integrator output swing compared to the conventional direct path compensation. This potentially allows to avoid the swing, quantizer scaling and noise trade-offs due to ELD in state of the art designs.

This paper presents an extensive study of pseudo-resistors for usage in biomedical applications like implantable brain-machine-interfaces. In order to suppress DC offsets while simultaneously recording signals ranging into the sub-hertz domain, low-frequency high-pass filters are employed in the frontend of neural recording integrated circuitry. With the limited ranges of on-chip passives, no sub-hertz corner frequencies are possible. Switch-capacitor resistances and resistor duty-cycling are infeasible since these techniques cannot provide the required absolute resistance values. Concepts like multi-rate duty-cycled resistors have been successfully demonstrated, but require clock signals, which can lead to noise back-folding, especially in chopped systems. Pseudo-resistors utilize the off-resistance of MOSFETs to form extraordinary large resistors, and are thus capable of providing the required corner frequency in a very area efficient way. The drawbacks are limited linearity, and deviations of 100x over process variation and temperature were reported in prior art. In this brief we show measurement results from more than 160 dice (>5400 recording channels) from 3 production runs to demonstrate that the variations are much less severe in realistic operating conditions, and that sufficient linearity can be achieved. Our experiments let us conclude that the usage of pseudo-resistors in neural recording applications can in fact be used to robustly realize the required HP corner frequency for electrode DC offset blocking.

The performance of a 0-X MASH DSM is primarily defined by the DSM noise-shaping and the inter-stage gain (ISG). Due to system specification like modulator order and OSR, the DSM noise shaping is limited. All further performance in the 0-X MASH modulator is achieved by setting a large ISG, which amplifies the residue signal before it is processed by the fine stage DSM. This paper presents an analysis of the factors influencing the ISG and proposes measures, which can be used to maximize it. Most importantly, it is shown, that the CIFB DSM architecture is preferred, since the wideband residue overloads the CIFF architecture with its peaking OOB STF much earlier, thus CIFB results in more ISG and less internal swings. The presented analysis can be used as a guideline for achieving optimum performance in a 0-X MASH DSM and yielding the maximum SQNR.

This paper presents a mismatch error cancellation technique for high-resolution successive approximation register (SAR) analog-to-digital converter (ADC). The proposed technique that combines residue voltage oversampling and capacitors rotation significantly diminishes the impact of capacitor mismatch without calibration. A VCO-based comparator is adopted to achieve good noise performance with high energy efficiency. A 13-bit 1-MS/s SAR ADC is designed in a 180-nm CMOS technology to prove this technique. The post-layout simulated SAR ADC consumes $154.45 \mu \mathrm{W}$, achieves SNDR of 75.25 dB and SFDR of 90.34 dB at Nyquist input, resulting in a Schreier Figure of merit (FoM) of 170.35 dB.

In this paper, we present an integrator-differentiator transimpedance amplifier (I-D-TIA) with a dc compensation, which incorporates widely tunable multi-element pseudo-resistors (MEPRs) in its dc servo loop and ac signal path. The implemented MEPR in the dc path is continuously tunable from$460 \,\mathrm {k\Omega }$to$300 \,\mathrm {G\Omega }$allowing the TIA to process dc currents with a dynamic range of more than$100 \,\mathrm {dB}$. The MEPR in the differentiator ac signal path provides a tunable resistance between$0.3 \,\mathrm {M\Omega }$and$100 \,\mathrm {M\Omega }$, resulting in an overall ac transimpedance between$3 \,\mathrm {M\Omega }$and$1 \,\mathrm {G\Omega }$. For the lowest ac transimpedance, a bandwidth of$10 \,\mathrm {MHz}$is achieved. The TIA provides a minimum input-referred current noise density of$1.6\,\mathrm {fA}/\mathrm {\sqrt {Hz}}$. The implemented MEPR has been optimized regarding its high-frequency noise by minimizing its parasitic capacitances. The MEPR shows an inherent shot noise suppression such that its noise stays close to the theoretical thermal noise limit and significantly below the theoretical shot noise limit, even for large dc currents. By using a sub-VSS supply for the MEPR, the asymmetry in its output characteristic is greatly reduced, leading to a linear signal swing of$1.5\,\mathrm {V_{pp}}$with a THD below$1 \mathrm {\%}$on a$1.8-\mathrm {V}$supply. Thanks to this high linearity, large bandwidth, and high dc current dynamic range, the proposed TIA can be used in a wide variety of applications from high-sensitivity, low-bandwidth lock-in detection to transient current sensing with sub-microsecond timing resolutions.

The performance of Continuous Time Delta-Sigma Modulators (CT-AEMs) is limited by clock jitter in the outermost feedback DAC. As one solution, FIR-DACs have been introduced to improve the modulators jitter robustness. In literature, those FIR-DACs have been described with equal coefficients for all taps. This paper investigates the effect of using non-equal symmetric taps on the modulators performance. A comparison between the two FIR filters (equal and non-equal symmetric taps) regarding jitter immunity, sensitivity to coefficient mismatch, complexity of the filters and the required compensation filter are presented. Furthermore, the effect of the FIR filters on the modulators dynamic requirements and its STF are discussed. The paper shows that symmetric non-equal coefficients outperform the equal coefficients configuration in all aspects without sacrificing hardware complexity, resulting in an extension of the modulator's jitter immunity limit and reduction of power consumption.

A well-known problem when using Physical Unclonable Functions for secret key generation and storage, is the instability of PUF responses due to environmental conditions like temperature variations. Using Ring Oscillator PUFs (RO-PUFs), a response bit is usually derived based on the comparison of a RO frequency with either a threshold or another RO frequency. Especially for multi-valued PUFs it is of importance to decrease RO frequency errors before digitization. Otherwise, these errors can result in a huge amount of bit-flips. To counteract environmental influence in the reproduction phase, we propose to map a frequency, which might be remeasured under a temperature condition different from initialization, closer to the initial frequency by using a method based on polynomial interpolation. This paper presents how such an approach can decrease errors in multi-valued responses and evaluates the error based on the used polynomial order and thus complexity.

This paper analyzes the effect of signal transfer function (STF) peaking in continuous-time (CT) Delta-Sigma- Modulators (DSMs) arising from excess loop delay (ELD) and its compensation. Starting from a generic model, the origin of different contributors to STF peaking are revised, namely noise transfer function (NTF) peaking due to aggressive noise shaping, instability from uncompensated delay as well as forward loop filter zeros in cascade-of-integrators with distributed feedforward (CIFF) modulators. The shift of forward loop filter zeros as a result of ELD compensation is shown intuitively for a 3rd order example, while system-level simulations of various 2nd, 3rd and 4th order CT single-loop modulators confirm increased STF peaking in the above stated scenarios.

This work presents an approach for a complete noise analysis and optimization flow for switched-capacitor MEMS readout frontend circuits. The flow starts with an early noise evaluation on a high abstraction level. The evaluation is performed using analytical calculations as well as simulations in MATLAB/Simulink. The presented approach is applied to a charge-balanced readout circuit example, which is eventually simulated at transistor level and measured. The results of the analytical calculations, the Simulink and the transistor-level simulations as well as the measurements are then compared showing the accuracy of the approach. Furthermore, an analysis is carried out on how to decrease the noise by identifying the most impacting parameters of the circuit and by evaluating the influence of a boxcar sampler in the charge-balanced readout circuit.

Physical unclonable functions (PUFs) produce responses by exploiting randomness that intrinsically occurs in integrated circuits due to uncontrollable variations in the manufacturing process of physical items. It is common practice that PUFs generate binary responses. Recently, it has been proposed to extract symbols from a higher-order alphabet in order to increase the length of the final response. In this paper, coding for this concept of multi-valued PUFs (MV-PUFs) is derived from the analogy to pulse-amplitude modulation in digital communications. To that end, based on ROPUF measurement data, we replace the classical binary symmetric channel model by a suited additive white Gaussian noise model. Consequently, the hard-input binary channel coding scheme is replaced by methods from coded modulation, utilizing the soft output. In addition, the functionality of helper data, which are required to stabilize noisy PUF responses, is transferred to the multi-valued case. By applying the designed methods to the available measurement data we eventually show that imagining the analog PUF output as$M$-ary amplitude-shift keying symbols observed over an AWGN channel, both the extracted entropy per response symbol and the reliability of the final key can be increased.

Intersymbol interference (ISI) plays an important role in the performance of continuous time delta-sigma modulators(CT-ΔΣM). Different techniques, such as return-to-zero DAC, ISI-shaping or calibration, were proposed in literature to tackle ISI in CT-ΔΣM. This paper investigates the effect of ISI in the outermost feedback digital-to-analog converter (DAC) for three different DAC structures; a single-bit DAC (SB), a multi-bit DAC (MB) and a FIR DAC. For each case, Monte-Carlo simulations were performed plotting the SFDR and SNDR for different rise/fall time mismatch percentages. The paper shows that DAC element mismatch due to rise and fall time variations in MB-DACs is more severe than ISI. However, for FIR-DAC the contrary is observed, the degradation in the performance due to ISI in FIR-DAC can be as severe as in SB-DACs when all FIR-taps are matched with regards to rise/fall time.

In transmitters of cellular modems of many generations, feedback receivers (FBR) have been playing an important role in controlling the quality of the transmit signal. What set feedback receivers apart from other receivers (RX) are their requirements needed to provide measurements of the transmitter (TX) on-chip while not consuming significant extra power. Whereas many publications and proposed architectures for normal receivers exist, there is very little literature dedicated for feedback receivers. This paper explains the requirements of cellular modems' feedback receivers, describes some of its design challenges with examples based on the 5G NR standard, and outlines some of the state-of-the-arts descriptions. This paper should serve as a motivation and basis for other researchers to contribute to the field.

This demo shows the automated characterization of Xilinx Zynq FPGAs on the Digilent Zybo with the help of a framework based on Partial Reconfiguration. Fine-granular measurements of the whole chip area reveals several aspects which have to be taken into account for PUF system design on these devices. In this demo, the visitor will get to know the general measurement approach and explanations about the provided results. With the help of a python based tool, the visitor can experience the workflow first-hand, generate their own measurements and use them to differentiate a single board from a set of multiple other boards. Further in-sight can be gained by analysis of the different statistical metrics and by combining measurements from multiple boards.

Physical Unclonable Functions utilize random variations from manufacturing to generate unpredictable, yet repeat-able fingerprints of devices for usage in a hardware cryptographic context. Most often, they are dedicated electrical circuits in integrated devices and thus occupy additional space while only few implementations exploiting already existing hardware. In this work, we analyze the possibility to extract hardware unique fingerprints from the distinct differential nonlinearities of analog-to-digital converters, which are present in almost every system. The transfer curves from measuring a large set of low-cost analog-to-digital converters with 12 bit resolution are analyzed regarding their quality as system fingerprints. Additional postprocessing methods are investigated for further improvement of the uniqueness metrics. The fingerprints are optimized to a perfect inter-hamming distance of 50% and close-to-maximum entropy. These improvements come at the cost of a reduced number of extracted bits, yet the minimum achieved number of 440 bits is sufficient for secret key generation. By thresholding and consequently avoiding unstable positions in the extracted bit-strings, the intra-hamming distance of unprocessed transfer curves could be reduced to less than 4%. Further measurements over a large temperature range shows that the error rate due to temperature drift never exceeds 13%.

Physical unclonable functions are integrated circuits well-known for their potential to replace dedicated secure storage of cryptographic keys. On FGPAs, ring-oscillators have received great attention as the most preferable implementation. Many measurement data sets have been published with large quantities of ring-oscillators on large quantities of chips. Yet, all these data sets are missing large quantities of readouts, which limits their usage for proving the efficiency of error correction algorithms. In this work, we present multiple different approaches of measurement control and readout extraction for external storage. We cover the full development process, beginning with slow extraction in early stages for maximum control up to final extraction with automated high-speed designs. Targeting a Zynq-7000 architecture, the final design extracts 3800 · 10000 readouts within 8.04 s, which relates to a data extraction rate of 36 Mbit/s. In comparison to an early stage design, which took 452.91s for the same measurement, a reduction in total run time of 98.2% was achieved.

Recent state-of-the-art designs have shown that high jitter robustness and low integrator dynamics, thus better linearity can be achieved in a single-bit continuous-time (CT) delta-sigma (ΔΣ) modulator by adapting a finite impulse response (FIR) filter in the feedback digital-to-analog converter (DAC). However, when applying this to CT incremental ΔΣ modulators, after each periodic reset of the loop-filter, the output of each FIR tap is unrelated to the input signal and a certain amount of time is needed to settle back to a normal operation. This results in a severe swing overshoots at the output of the integrators in the initial phase of every incremental ΔΣ conversion cycle, which limits the dynamic range (DR) of the modulator and thus counteracts the benefits of the FIR DAC. This paper describes the challenges that come with acquiring an FIR DAC in an incremental ΔΣ modulator. Additionally, two design techniques are shown to mitigate the swing overshoots and achieve a normal operation of the modulator. This allows higher number of FIR taps to be used in an incremental ΔΣ modulator, which is very beneficial to promote high speed/resolution designs.

Modern neuromodulation systems feature parallel low-noise recording on a large number of channels, limiting the available area per channel. This has made chopper-stabilization the modality of choice for many recently published implementations. To tackle the issue of decreased input impedance, the auxiliary path boosting scheme can be used, which minimizes the amount of charge drawn from the electrode by precharging the input capacitors through a voltage buffer. However, the offset of the buffer translates to a deterministic amount of charge per time that is transfered to the electrodes and accelerates electrode aging. If blocking capacitors are used as a safety feature, the offset-induced charge can lead to a voltage drift due to charge accumulation, that slowly saturates the buffers. This paper presents a voltage buffer that uses a self-compensation scheme to reduce the time-averaged offset to sub - 20 μV, thereby minimizing excess charge.

Bandpass ΣΔ modulators using LC resonators typically require an active Q-enhancement circuit in order to achieve a higher resolution. However, the Q-enhancement circuit operating at GHz range suffers from finite speed due to power constraints. In this paper, the effects of finite gain-bandwidth of the Q-enhancement circuit in bandpass ΣΔ modulators are analyzed, and a mathematical model is derived. The model quantitatively clarifies the two kinds of distortion in the noise transfer function due to finite gain-bandwidth, namely a shift of the in-band zeros and an out-of-band peaking. Compensation is then applied such that the original noise shaping is retained. Consequently, Q-enhancement circuit can be designed with a smaller gain-bandwidth in order to reduce its power consumption.

Dual quantization is an effective method to combine the benefit of single bit quantization, which results in inherently linearized DAC, and multibit quantization, which results in lower sampling rate. However, extra noise inserted in the loop due to requantization needs to be shaped out of the signal band to ensure the inband characteristics to remain as without the dual quantization. However, this additional shaping may result in extra noise injected into out of the band, which, if not filtered properly, may affect the loop dynamics and stability. Prior arts have used FIR filtering to filter out this additional digital quantization noise but in an ineffective way. In this paper, we show that the cutoff of the FIR filter can be reduced to much lower than Nyquist bandwidth(fs/2) and can be brought close to the signal bandwidth of the modulator resulting in a further improved performance.

Physical Unclonable Functions (PUFs) offer the possibility to produce unique fingerprints for integrated circuits. As raw PUF responses are affected by noise, some post-processing steps are necessary. We present a coding chain test framework for PUFs on Field Programmable Gate Arrays. The framework allows easy exchange, evaluation and comparison of different PUF implementations, coding algorithms and other chain modules. For a testing framework, the execution time of the evaluated algorithm is a bottleneck, since a huge amount of runs are supposed to be done. Hence, we additionally present a new type of Reed-Muller decoder hardware architecture using parallel modules to speed up the decoding process. The decoding time could be decreased by 95% in comparison to existing implementations at the cost of 41 times higher slice count.

Incremental Sigma-Delta (ΣΔ) modulators inherit internal oversampling and noise-shaping properties of a conventional ΣΔ modulator. However, by resetting its internal states, as well as the digital reconstruction filter after certain number of clock cycles, a sample-by-sample conversion behavior is obtained and the modulator can be considered as a Nyquist-rate converter. Multibit architectures allow for low oversampling ratios and can be very attractive for high speed applications. Yet, it comes with digital-to-analog converter (DAC) linearity concerns and commonly used linearization techniques such as dynamic element matching are inefficient when acquired in an Incremental ΣΔ modulator, due to the resetting environment and especially for very low OSRs. This paper presents an enhanced incremental sturdy multi-stage noise-shaping ΣΔ modulator structure, which utilizes a variable quantizer bit width in the second stage for linearity improvement. The behavioral simulations of the proposed architecture show its robustness against DAC mismatch, achieving 25 dB improvement in total harmonic distortion in the presence of 0.1% DAC element mismatch with an OSR of 35.

Electrical Impedance Spectroscopy (EIS) is a popular method for investigating tissue properties. Implementing the signal generator for EIS measurements with a suitable excitation signal type is thereby one of the two system components. The choice of the excitation signal defines the measurement speed, signal-to-noise ratio (SNR), total area and power consumption of the system, and many more properties. Signal types such as analog single-tone, analog multi-tone, linear feedback shift registers (LFSR), and single-tone Sigma Delta Modulated (ΣΔM) are proposed in the state of the art. In this work an EIS setup is implemented and successfully tested with all the mentioned signal types to evaluate their properties on impedance models as well as in vitro cell layers. It is proposed to combine the ΣΔM with the multi-tone excitation signal yielding a very versatile excitation generator. Multi-tone ΣΔM are as fast as analog multi-tones, while benefiting from a binary output and thus less system complexity. The implemented EIS setup is used to perform EIS measurement for biological samples. The results show a very good matching with the reference for all the excitation signals.

This demo shows the automated high-level design process of continuous-time bandpass ΣΔ modulators with the web-based design tool www.sigma-delta.de. The design methodology presented in this demo is based on a heuristic search which allows to directly account for major non-idealities as excess-loop-delay, finite bandwidth and finite DC gain. In contrast to other state-of-the-art design methodologies, it allows to include specifications for the STF and is not just focused on the optimization of the NTF in order to achieve a high SNR. In this demo the visitors get to know the capabilities of the tool and a general insight is given with the possibility of hands-on experience. The workflow - with a fast response such that the visitors can generate their own modulators in real time - is illustrated with matching examples.

In this paper, we present a new strategy for energy-efficient and noise-aware LC tank oscillator design. In contrast to commonly used design concepts, the proposed method fully accounts for the oscillator nonlinearity. To this end, the proposed approach uses a perturbation theory based approach to obtain nonlinear estimates of both the oscillation amplitude and the oscillation frequency. Then, to model the oscillator phase noise, a variant of the stochastic averaging method initially proposed by Stratonovich is used to obtain an analytical model of the oscillator phase and frequency noise in the white noise regime. From these analytical expressions, we identify the oscillator bias current and coil inductance as important design parameters and show how a single 3D-phase noise plot can be used to obtain a very good starting point for a final oscillator optimization using numerical simulations. Finally, the proposed method is validated using an example design in a 130 nm CMOS technology.

This paper presents a state-of-the-art overview and recent advances on circuit and system level design methods and EDA tools for the automation and optimization of Delta-Sigma (ΔΣ) modulators. Main synthesis strategies and techniques are highlighted, putting emphasis on those aspects, which need to be taken into account in order to maximize the performance of ΔΣconverters, while keeping computational efficiency high. Based on the comparison of the approaches considered in this survey, the authors try to answer, where man or machine can come in1.

The jitter sensitivity of continuous-time ΣΔ modulators is well known. It becomes an even more severe performance bottleneck in receiver applications, when out-of-band interferers are present together with colored phase noise. Bandpass ΣΔ modulators, as a competitive candidate for software-defined radios, are typically considered to be disadvantageous regarding jitter, and it can be shown that they are at least similarly affected by jitter as the mixer in a direct conversion receiver. In this paper, an analog interferer suppression technique is presented for bandpass ΣΔ modulators, which allows them to be more tolerant to interferer induced jitter error, thereby relaxing the overall clock phase noise requirements compared to other receiver architectures. The proposed technique is also combined with a previously published digital interferer suppression technique in order to provide suppression over a larger frequency range.

Like every integrated circuit, Arbiter-PUFs suffer from any ambience variations such as electrical noise, supply voltage variations and temperature fluctuations. In this work, we show that most bit-errors are related to small phase differences, for which noise dominates the readout bit value. We present an approach eliminating this influence by modifying the arbitration circuit part into an eye-opening oscillator. By utilizing the deadzone of two D-Flip-Flops, the decision about the response is delayed until the phase difference becomes significant enough. With this modification, we could increase the PUFs initial bit-error rate of 3.31% to almost zero. We also highlight important design choices for this solution, like the setup-time of the D-Flip-Flops and the minimum number of enforced oscillations.

Time interleaving is one of the prominent ways to increase the operating speed of data converters. However, mis-match artifacts among the time interleaving sections impair the performance benefits obtained from the use of time interleaving. CTDSMs with time interleaved quantizers are particularly affected by the gain mismatch in the time interleaved feedback DAC. We present a circuit technique to eliminate this adverse effect of the gain mismatch between time interleaved sections in 2×-time interleaved quantizers. The proposed technique involves the use of a three state DAC as a feedback DAC element. The simulations results obtained from the schematic level implementation of the proposed three state DAC in 40nm CMOS process demonstrate the efficacy of the presented idea.

A delta-sigma modulator architecture reducing the impact of the digital-to-analog converter (DAC) non-linearity in a multi-bit delta-sigma DAC is presented. By cascading and deterministic dithering, only small signals are processed by the multi-bit DAC, thus a large dynamic range can be maintained; by suppressing the out-of-band noise before being processed by the multi-bit DAC, less shaped-noise gets inter-modulated by the non-linear DAC, thus the raise of noise floor is reduced. The proposed architecture provides a practical way to implement a high-resolution multi-bit delta-sigma DAC at low over-sampling rate (OSR). System level simulations in MATLAB show that an average ENOB=14.5-bits can be achieved with 0.2% (standard deviation) DAC element mismatch at OSR = 10.

In this paper, a comparison between three different current readouts for micro-potentiostats is presented: resistive transimpedance amplifier (R-TIA), capacitive transimpedance amplifier (C-TIA), and current-mode continuous-time sigma-delta modulator (Current-CTSDM). The comparison is carried out on the signal transfer function, the required amplifier gain-bandwidth (GBW), its input referred noise current, required area and power, and dynamic range. Each approach and its limitations are separately discussed. The three systems have been simulated using VerilogA models and the results are compared. It is shown that each system comes with its own limitations, however current-mode CTSDM are more beneficial due to their intrinsic digitization.

Clock jitter sensitivity is a well-known drawback of continuous-time ΣΔ modulators. Although there exist various methods to alleviate the jitter influence, most are only effective in reducing noise incurred by out-of-band quantization noise. However, due to the steadily increasing signal frequency in receiver applications, the dominant jitter influence rather originates from the mixing between the close to in-band interferers and the close-in clock phase noise, either in a mixer or in the DAC of a bandpass ΣΔ modulator. This mixing results in additional in-band noise which cannot be reduced by existing solutions. In this paper, we use a reconfigurable digital filtering method for close to in-band interferer suppression in bandpass ΣΔ modulators, and demonstrate its effectiveness in improving phase noise tolerance through simulation. Additionally, a technique to simplify the implementation of the digital filters is proposed.

In this paper, we discuss the requirements for an NMR setup to allow for combined NMR microscopy and spectroscopy using planar microcoils to study metabolic processes in vivo. Here, NMR is particularly suitable because — unlike most other currently used methods — it can deliver structural information as well as qualitative and quantitative information about the molecules involved in cellular processes. More specifically, based on the reciprocity principle, we derive why previously presented fully-integrated CMOS receivers using on-chip NMR coils in receive-only mode are not suitable for in-vivo spectroscopy applications. As a solution to this problem, we propose the use of fully-integrated transceivers which use their on-chip planar microcoils in TX/RX mode as an ideal tool for combined in-vivo NMR imaging and spectroscopy. Measurements using a planar coil on a thin silicon substrate validate the theoretical analysis.

In this paper the automated design of continuous-time bandpass ΣΔ modulators with arbitrary signal-transfer-functions is described. State-of-the-art design methodologies rely on multiple transformations to obtain continuous-time bandpass modulators. Moreover, they are mainly focused on the NTF in order to achieve the required SNR. A design approach, which allows to realize a specified signal-transfer function is not known in the state-of-the-art. In contrast to that the web-based design tool www.sigma-delta.de allows STF engineering for bandpass modulators as first of its kind. The STF is optimized with regard to user defined specifications while the signal-to-noise ratio of the modulator is maximized. This work gives a general introduction to the tool and explains the features concerning bandpass modulators in detail together with corresponding examples.

Together with the increasingly demanding DAC, the design of the comparator introduces a big challenge for the implementation of high resolution SAR ADCs. Therefore, several state of the art works investigated improved comparator architectures aiming for higher resolution. However, those architectures in most cases resulted either in excessive power consumption or compromised conversion speed. For improved performance and power efficiency this paper proposes the use of two dynamic comparators in a 14-bit SAR ADC. The first coarse decisions are made by a low power comparator, while the second comparator applies an automatic noise reduction technique to perform accurate decisions around the LSB. The proposal includes SAR conversion which applies two switching schemes a monotonic and a differential one. The design is partially implemented and simulated on transistor level using a 40 nm CMOS technology. The ADC is operated with a sampling frequency of 1.6 MS/s and features an SNDR above 81 dB and an SFDR above 97 dB. The estimated power consumption of the two comparators is 44 μW and about 27 μW for the DAC reference.

Fast and high-resolution scanning ion-conductance microscopy (SICM) experiments require a high speed, low noise and low distortion transimpedance amplifier (TIA) as interface circuit. Recent high performance TIAs utilize capacitive feedback. However, their inability to treat DC currents renders them unfavorable for SICM applications and resistive TIAs remain the best choice here. To address this problem, this paper presents an active MOS resistor with improved robustness and linearity to make it suitable for its use as feedback resistor in TIAs for SICM experiments. The presented device features PMOS transistors operating in weak inversion as pseudo-resistors to obtain reduced noise compared to ohmic resistors of the same value. A novel bias circuit is introduced which compensates process variations of the pseudo-resistor. Monte Carlo simulation shows a standard deviation of 3.6 % of the overall resistance. The connection of multiple pseudo-resistors in series, while preserving equal overall resistance, linearizes the I-V characteristic and decreases the total harmonic distortion to 0.26 %. The presented device is incorporated into a low noise and high speed TIA achieving a simulated SNDR of 49 dB over a bandwidth of 1 MHz enabling fast high-resolution topography imaging using SICM.

This paper presents a fully integrated, bidirectional, neural interface, which is composed of a high voltage (HV) stimulator and a low voltage (LV) neural front-end with active, spectral separation. The stimulator uses a supply of ±9V in order to achieve a high voltage compliance (VC), whereas the recorder has a supply voltage of 3 V for high power efficiency. By using a HV transistor to separate the two parts, a safe operation of stimulator and recorder with different supply voltages can be guaranteed. Thereby the presented architecture can deliver a maximum stimulation current of ±10mA with a dynamic range of 50 dB and a VC of ±8.2 V. The implemented recording part consumes 52 μW and achieves a simulated input referred noise of 2.5μVrms in the low frequency band from 0.1 Hz to 200 Hz and 3.1 μVrms in the high frequency band from 200 Hz to 7.5 kHz. The combined recorder/stimulator requires 0.378 mm2 per channel. A prototype of the interface has been implemented and manufactured in a standard 0.18 μm HV CMOS technology.

For two decades, Excess-Loop-Delay (ELD) is known to degrade the performance of continuous-time (CT) ΣΔ A/D converters. Many methods have been proposed to compensate for this effect, but for their implementation sophisticated knowledge in loop-filter design is necessary. The web-based design tool for CT ΣΔ modulators www.sigma-delta.de offers a straightforward integration of commonly used ELD compensation techniques in an early stage of the design process without the need of in depth knowledge of ΣΔ loop-filters. As the tool uses a heuristic search, based on a genetic algorithm within a parallel implementation on a GPU, it provides results with a very short response time. This paper presents the compensation techniques which are commonly implemented within the state of the art and shows their automatic application on architectural level by the design tool. Exemplary modulators are created and evaluated in a circuit level simulator. Further, the calculation of device parameters for a circuit-level simulator model, based on the coefficients obtained by the tool, is illustrated. Thereby, the usage of the developed and publicly available design tool for CT ΣΔ modulator is practically shown.

This paper describes a fundamental limitation of the implicit anti-aliasing filter in continuous-time feedback compensated sigma-delta modulators and a method to overcome it. This anti-aliasing filter can be used to relax an additionally required pre filtering stage. If a strong alias rejection is required, commonly used continuous-time feedback compensated sigma-delta modulators would need some pre-filtering or a large oversampling ratio. The described technique generates a notch at the sampling frequency to improve the performance of the antialiasing filter. This method is possible without additional active components or large oversampling ratios. It is also very robust against component mismatch.

We report on an experimental low power transcutaneous optical telemetric link (TOTL) for high speed biomedical data transfer. By decreasing the bandwidth to data rate ratio, a silicon photodiode with large active size can be used to significantly increase transmission efficiency as well as misalignment tolerance. Additionally, a custom-designed transimpedance amplifier (TIA) with low input referred noise and a modified on-off keying with a custom designed low power VCSEL (vertical cavity surface emitting laser) driver are used to further reduce the required power consumption. The proposed system transmits data up to 75 Mbps through 6 mm thick tissue, in the presence of a 4 mm misalignment while achieving a BER better than 10−5, with a power consumption lower than 2.8 mW.

In this work, an unscented Kalman filter with improved numerical properties is shown to be able to simultaneously estimate the major nonidealities of continuous-time sigma-delta modulators. Circuit imperfections in sigma-delta modulators like, e.g., nonlinearities in the feedback digital-to-analog converters are known to highly reduce the modulators's performance. The state of the art shows several techniques to compensate for some of these nonidealities, whereby most of the methods only focus on single parameters or can only be applied to specific modulator structures. The presented method is capable of estimating the most serious nonideal circuit parameters concurrently whilst not being limited to specific modulator structures.

We present in this paper the design of a wide-band efficiency-enhanced CMOS rectifier. A novel semi-active diode is proposed to minimize both the diode forward voltage drop and the reverse leakage current. This is achieved by dynamically configuring the rectification device as a threshold compensated diode in the on-state while a standard MOS diode in the offstate, respectively. The proposed rectifier is implemented in a 0.35μm 4M/2P standard CMOS process. In simulation, with 5.5V AC input at 13.56MHz, the rectifier outputs 4.94V DC voltage across a 1.2kΩ load resistor, achieving 87% power conversion efficiency (PCE) and 90% voltage conversion efficiency (VCE). The PCE and VCE can be maintained from 1MHz to 20MHz input frequency, with only 3% deviation in the PCE and 2% deviation in the VCE. In addition, the performance of the rectifier is self-compensated over temperature and process. From -40°C to +130°C, the simulated VCE varies within 2% from 89.6% to 87.7%, while the PCE stays almost constant at 86%. With 200 Monte Carlo samples, the standard deviation in the PCE and VCE are as low as 0.56% and 0.57%, respectively.

This paper shows a neural stimulator with 15V supply voltage combined with a neural low-noise amplifier (LNA) with a supply of ±1.65V around the common mode voltage (VCM) of 7.5V. In most implementations, the stimulator and recorder use the same supply domain, thus either leading to low voltage compliance (VC) for the stimulator or to high power consumption in the recorder. Obviously, a separation of both is the preferable choice, but comes with the challenge of effective protection of the low voltage (LV) sensitive input nodes of the recorder. A high voltage (HV) transistor used as a switch between the two parts enables different supply voltages for stimulator and recorder. Thus, a high current stimulator with high VC can be combined with a high efficient LV neural recorder. The presented implementation shows a stimulator with a maximum stimulation current of ±15mA with 5-bit resolution out of a 15V supply. The recording part consists of a LNA with a VCM of 7.5V and a supply voltage of ±1.65V around VCM - VDDLNA=9.15V and VSSLNA=5.85V. It consumes only 11.8μW and achieves an input referred root-mean-square (RMS) noise of 5.5μV in the frequency band of 1Hz to 100kHz. The design is implemented and simulated in a 0.18μm HV technology.

In this paper, a new method of calculating the transfer functions of continuous-time (CT) sigma-delta modulators is presented. The common approach of calculating the transfer functions is to analyze a discrete-time (DT) equivalent of the CT loop filter together with the CT input filter path. The DT equivalent is most commonly obtained via either the impulse invariant or the modified Z-transformation. This work provides a numerical alternative to these methods, based on DT simulation models, which can be obtained by a previously published method of DT simulating CT sigma-delta modulators, called lifting. This allows incorporating all linear-time-invariant non-idealities, such as finite DC gains and gain-bandwidths in the integrator stages, as well as excess-loop-delay and any waveform shape in the digital-to-analog converter.

This paper considers the implementation of a continuous-time low-pass single-bit ΔΣ analog-digital converter (ADC) for radar applications. By taking advantage of the high transit frequency of a 0.25μm SiGe BiCMOS technology, the 3rd-order modulator operates at 1.92GHz and achieves 77.8dB SNDR within a bandwidth of 15MHz, when simulating the sensitive circuit parts on transistor level. Thanks to the inherent linearity of single-bit digital-analog converter (DAC), high linearity of 90dB spurious-free dynamic range (SFDR) can be achieved.

This paper presents the design of a 4 bit flash quantizer with an alternative low kickback, wide DC range input clocked core comparator. The quantizer is demonstrated within a third order continuous time (CT) ΔΣ modulator operating at an fSof 1GHz with an OSR of only 10. In using the proposed clocked core and output latch, a reduction in current consumption within all preamplifiers and resistor ladder can be established. The schematic based flash quantizer is designed in a 1.2V supply 90nm TMSC process, consumes an overall 1.47 mW, and has a decision time of 132 ps. As demonstrating within the exemplary ΔΣ modulator, a coefficient dependent SNDR of 69.8 dB within a 50MHz bandwidth is achieved. When comparing to other state of the art ΔΣ modulator quantizers it achieves one of the lowest power consumptions.

This paper presents the design of an fully differential current steering DAC for a continuous time (CT) ΔΣ modulators with an all native switched DAC cell. In using the proposed cell a lower load capacitance on the virtual ground node of the integrator, reduced charge injection and clock feed-through is obtained when compared to the commonly used NMOS/PMOS DAC cell, thus resulting in an improved performance and lower ISI sensitivity. The native switched DAC is functionally demonstrated within a third order CT ΔΣ modulator operating at an fSof 1GHz with an OSR of 20. The schematic based DAC is designed in a 1.2V 90nm TMSC process including V-I biasing to track the modulator input resistance. Within the explemary ΔΣ modulator an SNDR of 79.12dB and SFDR of 93.44dB within a 25MHz bandwidth is achieved while only being limited by the thermal input noise of the modulator. When comparing to the commonly used NMOS/PMOS switched cell, an improvement of 3dB and 7.3dB in SNDR and SFDR is achieved with the same area and current.

This paper presents the system level model of a transcutaneous optical telemetric link (TOTL) system for neural recording. Varieties of noise sources are characterized. Power distribution is described by means of Gaussian model approximation. Strategies for designing of the optical receiver that maximize signal to noise ratio (SNR) are discussed. The system level model presented here allows designers to compromise the TOTL receiver design for certain constraints: data rate, power consumption, thickness of tissue and receiver size.

In this work, a method for the concurrent estimation of nonidealities in continuous-time sigma-delta modulators is presented. Several nonidealities can degrade the performance of a sigma-delta modulator, even up to instability of the entire circuit. However, if these nonidealities are known, it is possible to correct for most of them - either in the analog or digital domain. In the past, many techniques for corrections of errors in sigma-delta modulators have been presented. Although these works show good results, most are only able to work on a single or few nonidealities simultaneously. In this paper, a feasible approach for estimating several nonidealities in a joint fashion has been applied to estimate some of the most prominent errors in a continuous-time sigma-delta modulator.

This paper describes a method to improve the linearity, area or SNR of feedback (FB) compensated Sigma-Delta (ΣΔ) modulators. These performance limiting factors are often related to the outer loop feedback DAC or to the 1stintegrator of the ΣΔ-modulator in a FB-compensated modulator. This work focuses on improvements of the 1stintegrator. The origin of these problems is the output swing of the 1stintegrator, which includes and is dominated by the input signal. This problem is usually solved by increasing the capacitor size of this integrator, which results in an increased area and power. Another common solution is to use a feed-forward (FF) compensated ΣΔ-modulator, where basically only quantization noise is processed by the 1stintegrator. However the drawback of this approach is a usually wide bandwidth and peaking of the modulator's signal transfer function (STF). The proposed solution greatly reduces signal swing at the 1stintegrator, by not affecting the STF. Thus, it takes the advantages of the FF-topology, by keeping the advantages of the FB-topology.

In this paper we present a new architecture for PLL-based high-speed demodulation of frequency-modulated AFM signals. In our approach, we use single-sideband frequency up-conversion to translate the AFM signal from the position sensitive detector to a fixed intermediate frequency of 10 MHz. In this way, we fully benefit from the excellent noise performance of PLL-based FM demodulators still avoiding the intrinsic bandwidth limitation of such systems. Furthermore, the system becomes independent of the cantilever's resonance frequency. To investigate if the additional noise introduced by the single-sideband upconverter degrades the system noise figure we present a model of the AM-to-FM noise conversion in the PLL phase detector. Using this model, we can predict an upper corner frequency for the demodulation bandwidth above which the converted noise from the single-sideband upconverter becomes the dominant noise source and therefore begins to deteriorate the overall system performance. The approach is validated by measured data obtained with a PCB-based prototype implementing the proposed demodulator architecture.

This paper presents an integrated neural stimulator with highly efficient power management solution, which is intended for a 1024 channel epi-retinal implant. The stimulator features an adaptive high quality LC matching network that compensates for the process variation in the resonance frequency of the inductive receiver and maximizes the link power transmission efficiency. Transcutaneous closed-loop power control is realized that enables optimum power transfer in spite of the coupling variation as well as the variation in the stimulation threshold/current. Finally, a programmable adaptive supply in the high voltage (HV) domain is implemented so to minimize the power dissipation during the active stimulation mode in terms of stimulus current/electrode impedance inconsistencies. The stimulator prototype is designed in AMS 0.35μm HV CMOS technology. In simulation, the power transmission efficiency of the telemetric link is improved by a factor of 2 by the resonance compensation circuits. In addition, automatic supply voltage adaptation of the stimulator from 13.1V to 8V has been achieved, resulting in maximum power saving of 40% for the implantable circuit.

A fully differential front-end circuit for a neural recording system with spike and Local Field Potential (LFP) separation by means of switched capacitor (SC) filters is reported in this paper. In many neural recording chips the transmitter is the most power hungry element and defines the number of channels on a chip. With a separation of the neural signal, it is possible to reduce the data rate and so the power consumption of the transmitter without any reduction of resolution in the quantized signal. The system consists of a low-noise-amplifier (LNA), an anti-aliasing-filter with tunable gain and a corner frequency at 50kHz to enable SC circuits with a clock frequency of 100kHz. Two SC biquad filters with tunable gain and tunable corner frequency are implemented to split the spikes and the LFP from each other and to amplify the sub signals to the full swing. Both channels provide an input referred noise of 3.8μVrms in the passband and the whole front-end circuit has a power dissipation of 52μW. A prototype is fabricated in a standard 0.18μm CMOS process and tested successfully.

This paper describes implementation issues for high speed 2-step-flash analog-to-digital converters (ADCs) without digital correction. A novel implementation for a multiplying digital-to-analog converter (MDAC) is described, which is a sample-and-hold amplifier, which includes a DAC, residue amplification and correlated double sampling (CDS), thereby omitting two-phase compensation differences. No digital correction is needed because linearity of the 2-step-flash ADC is provided by a capacitor-array matching and CDS prevents missing codes due to offset in the MDAC.

In this paper we present a correlation based error estimation technique using a residual test signal for the linearization of multibit feedback DACs of lowpass and bandpass Delta-Sigma analog-to-digital converters. Using residual test signal insertion allows operating in background with only limited loss in peak performance during test. Opposed to dynamic element matching techniques, which are limited by the intrinsic nonlinearities in the feedback DAC, the presented method recovers the performance of highly nonlinear systems back to their ideal resolution.

We review in this paper a new class of integrated CMOS rectifiers with improved PVT-compensated efficiency and propose also a new voltage quadrupler. By utilizing a threshold compensation technique, the presented circuits are able to achieve both high voltage conversion efficiency (VCE) and power conversion efficiency (PCE) with only standard threshold devices at low input amplitudes. Besides, the performance of the rectifiers is selfcompensated over process and temperature, which is achieved by precisely tracking the diode threshold drift with an auxiliary dummy. The rectifiers are implemented in AMS 0.35μm 4M/2P standard CMOS process and the simulated performance is shown at an input frequency of 13.56MHz. For the proposed voltage quadrupler, at 0.8V input amplitude and 2kΩ load resistor, output voltage of 1.52V can be achieved with VCE and PCE of 48% and 49%, respectively. As compared to previously published results, the improvement is up to 358% in VCE and 351% in PCE. Besides, the maximum deviation in its output voltage is as low as 162mV over 100°C temperature span, which outperforms the conventional structure by almost an order of magnitude.

This paper presents a 2.4GHz super-regeneration amplifier with capacitively-loaded integrated transmission line for a short range RF-pulse width transceiver. The degenerative quenching technique is employed in the super-regenerative amplifier to improve the linearity and reduces the sensitivity of negative transconductance (GM) to the bias current. It also reduces the direct coupling of the high frequency quenching pattern to the resonator and the negative GM stage. The capacitively-loaded integrated transmission line reduces the phase noise in transmit and receive modes. A test structure of the amplifier has been implemented in 0.25um BiCMOS technology. The amplifier consumes 1.2mA and 1.5mA from 2.5V supply in transmit and receive mode for a data rate of 20Mb/s and a sensitivity of -95dBm.

A digital tuning approach for adjusting the frequency of a resonator in a bandpass integrated transmission-line based SDM (BP-ITLSDM) is presented. The resonators are tuned by switching the length of an integrated transmission line (ITL) instead of the conventional varactor tuning. It makes the compensation process for the finite gain bandwidth (GBW) of transconductances independent from the tuning process of the resonator. Additionally, the same resonator gain is achieved at different tuned frequencies. To reduce the effect of parasitics and digital control patterns, common mode signal switching (CMS) is employed. The simulations are performed for a 2.5GHz resonator using a 16-segmented switchable ITL with unit length of 430um. A frequency tuning range of 1.5GHz and a finite GBW compensating range up to half of the sampling rate 10GHz is achieved in a 0.25um BiCMOS SiGe technology.

This paper presents a method to design continuous-time ΣΔ modulator with reduced peaking of the signal transfer function (STF). It is demonstrated that the approach is suitable for designing a flat STF while the anti-aliasing properties of the continuous time system can be retained. In addition, the presented method reduces the number of additional circuit elements needed for a flat STF frequency response. Experimental verification of the approach is presented.

This paper presents an approach to analyse the stability of continuous time ΣΔ data converters and shows a new method to define optimized parameter sets without a large number of simulations. Thereby the converter is described as a switched system. The presented analysis is based on a state space description which is utilized to express the properties of a stable behaviour. It is shown how the analysis method can be used to optimize the filter coefficients of the modulator by scaling the integrators outputs.

This paper proposes a multi-standard transceiver architecture, based on UWB impulse transmitter and 402-to-405MHz super-regenerative receiver for medical implant devices. This architecture eliminates the requirement of frequency synthesizer and power amplifier at transmitter side and LNA, mixers, IF amplifiers and ADCs at receiver side of implant transceiver. The test structure of transceiver has been implemented on 0.18μm CMOS technology. The UWB impulse transmitter consumes 0.3mW from 1.5V supply at the data rate of 500Kbits/s. The 402-to-405MHz super-regenerative receiver consumes 0.5mW at the data rate of 120Kbits/s and sensitivity of -95dBm.

This paper presents different alternatives for a hardware realization of a previously proposed correlation based background error estimation and correction technique. The technique is used to linearize the unit elements in the feedback DAC of a ΔΣ analog-to-digital converter (ΔΣ ADC). General system simplifications to reduce the necessary hardware are presented and verified by simulations. The hardware needed to realize key parts of the method-with the simplifications included-is compared between the different implementation alternatives. The hardware comparison is done for gate level implementations of an exemplary modulator, which is combined with the background estimation and correction system. Finally, the most suitable structure for an implementation is identified.

The feasibility and design guidelines for implementing integrated transmission-line based Sigma Delta modulators (ITLSDMs) have been studied. By a systematic design methodology for wireless frequency standards, the practical issues of realizing ITLSDMs such as different semiconductor technologies, performance, area and power consumption have been addressed. Having compared the different technologies and types of transmission lines (TLs), a typical 4th order bandpass SDM (BPSDM) as well as a 2nd order lowpass one (LPSDM) for a sampling frequency (fs) of 10GHz and a bandwidth (BW) of 78MHz have been simulated behaviorally to obtain the minimum circuit requirements for each architecture. An area estimation approach and an optimum realization method are finally proposed which lead to reduced chip area while keeping the performance constant.

This paper presents a Gm-C based field programmable analog array implemented in a 0.13 mum CMOS technology. It combines coarse adjustability via OTA and capacitor arrays, with fine tunability through floating gate bias current sources. It can instantiate almost arbitrarily complex continuous-time filters in a frequency range from 660 kHz to 135 MHz. Measurements show that filter coefficients can be tuned in steps of at least 1.5%, depending on filter type and bandwidth.

This paper presents measurement results on voltage and power efficient CMOS fully integrated rectifiers. Floating gate (FG) techniques are used to reduce the threshold voltage and thus the voltage drop over the rectifier. A three transistor single-poly FG diode is presented as basic element for half and full wave rectifiers. The rectifiers are implemented using a 0.35 mum high voltage CMOS technology. Measurements show a significantly higher output voltage and efficiency using programmed FG devices compared to non-programmed. Power efficiencies of up to 75% and 66% are measured for low and high voltage devices, respectively. The minimum operational input voltage of high voltage rectifiers is drastically reduced.

Charge balancing is a major concern in functional electrical stimulation, since any excess charge accumulation over time leads to electrolysis with electrode dissolution and tissue destruction. This paper presents a new active approach for charge balancing using long-term offset regulation. Therefore, the electrode voltage is briefly monitored after each stimulation cycle and checked if it remains within a predefined voltage range. If not, an offset current is adjusted in order to track the biphasic current mismatch in upcoming stimulations. This technique is compared to a previously introduced active charge balancer and both are verified through experiments on a platinum black electrode in 0.9% saline solution.

This paper presents a new approach for estimating nonidealities in unit element feedback digital-to-analog converters (DACs) of sigma-delta analog-to-digital converters (SigmaDelta ADCs). The presented method involves a background correlation technique to determine static and dynamic device mismatches as well as a way to digitally correct a modulators output. Simulations show that the method can be used to precisely estimate imperfections and improve non-ideal modulators up to their ideal resolution. The method is defined mathematically and verified by simulations.

In this paper, a new methodology for the automated design of one-bit internal quantizer SigmaDelta-modulators is presented. The core of the method is an NTF prototype generation in the DT-domain based on the quasilinear quantizer modeling, that maximizes the maximum stable amplitude (MSA) of the modulator while achieving a certain minimum peak SNDR. For CT-modulator's, this is followed by a DT-CT mapping of the loop filter in state-space. The improved MSA allows for higher circuit noise and thus greatly relaxes the area and power consumption constraints of the design. Simulation results at the end of the paper verify the validity of the method.

This paper reports on a Field Programmable Analog Array (FPAA) for high-frequency continuous-time analog filters. A rapid-prototyping hardware is presented, which implements a unique hexagonal topology of 55 tunable OTAs for reconfigurable instantiation of Gm-C filters in a 0.13 mum CMOS technology. It is the first analog array to achieve a bandwidth, which allows processing of intermediate frequencies used in communication systems. The maximum power dissipation is 70 mW at 1.2 V supply. The intuitive chip structure allows direct mapping of Gm-C filter schematics with up to 7 independent nodes, immediate download to the hardware, and evaluation of the working prototype.

This paper deals with an in-depth analysis of digital gain error compensation in continuous-time cascaded Sigma-Delta modulators. Illustrated by the example of a 2-1 cascaded modulator, it will be shown that this approach always restores the desired noise-shaping characteristic in cases where, except for the first stage, only first-order modulators are used in the cascade. However, a leakage term still exists which may increase the total in-band noise in case the first integrator of any stage in the cascade exhibits a gain variation. For any other architecture, the digital correction approach fails to truly compensate for gain errors as illustrated by the example of a 2-2 cascaded modulator. Low-order shaped quantization noise may then still determine the total in-band noise.

This paper presents improved integrated CMOS rectifiers using floating gate (FG) transistors. These FG rectifiers have a larger output voltage compared to standard realizations and work also at high input frequencies, which is essential for telemetric applications in the MHz range. Single-poly FGs are used, which can be produced in standard CMOS processes without special process options. The simulated performance is shown with 3.3, 5 and 20 V transistors at a frequency of 13.56 MHz. Using 20 V transistors, a voltage robust rectifier with e.g. 3.4 V output voltage from a 4 V input amplitude is realized. This is about 70% more output voltage compared to the same rectifier without FGs (Vout= 2 V). Programming of the FGs must be done only once.

The design of sub-threshold circuits is especially challenging due to the massive impact of process variations. These variabilities also heavily affect circuit timing, a problem only considered concerning combinational gates so far. In this paper the effects of process variations on flip-flop timing at sub-threshold voltages are analyzed based on extensive monte-carlo simulations. The results show that the usual timing-optimal definition of timing parameters needs to be replaced by a reliability-driven approach. The model is validated for sub- and near-threshold supply voltages and an approach for energy-optimal sizing is presented.

This paper investigates self-timed asynchronous design techniques for subthreshold digital circuits. In this voltage range extremely high voltage-dependent delay uncertainties arise which make the use of synchronous circuits rather inefficient or their reliability doubtful. Delay-line controlled circuits face these difficulties with self-timed operation with the disadvantage of necessary timing margins for proper operation. In this paper we discuss these necessary timing overheads and present our approach to their analysis and reduction to a minimum value by the use of circuit techniques allowing completion detection. Transistor-level simulation results for an entirely delay-adaptable counter under variable supply down to 200 mV are presented. Additionally an analytical comparison and simulation of timing and energy consumption of more complex subthreshold asynchronous circuits is shown. The outcome is that a combination of delay-line based circuits with circuits using completion detection is promising for applications where the supply voltages are at extremely low levels.

Circuit nonidealities such as real opamp behavior, coefficient mismatch, excess loop delay or jitter are known to drastically reduce the performance of continuous-time delta-sigma modulators. In this paper, the first step toward a successful correction and therewith compensation of these errors is presented: an online estimation of their real values based on an unscented Kalman filter. Contrary to the classical approach, which makes use of an extended Kalman filter, no linearization of the strongly nonlinear system equation has to be performed as a deterministic set of sampling points is used for the estimation. Therewith, the estimation performance is drastically increased, while the calculation effort still remains the same.

Field programmable analog filters (FPAAs) often lack the necessary bandwidth for high performance applications. This paper presents an FPAA based on Gm-C filters, which achieves routing without the use of transmission gates. Not only can the parameters of these filters be tuned, but also their order and structure. No additional capacitor is used for integration, only the MOS parasitic capacitances. A maximum bandwidth of 164 MHz has been achieved in simulations based on a 130 nm 1.2 V CMOS process. Distortion performance is high with a HD3 of less than -70dB for a 50mV@1MHz signal. Influences of parasitic capacitances are simulated using a test chip with 49 Gm-cells arranged in a hexagonal array.

This paper presents a method for the discrete-time (DT) simulation of continuous-time (CT) sigma-delta modulators. Via the application of lifting, correction values for each state variable of a modulator are calculated, which subsequently are used to calibrate online these state variables during a DT simulation of the CT system. At the sampling instants, the values of the DT state variables are thus exactly equalized to those of the given CT modulator while the time consuming CT simulation itself has been replaced by an efficient and rapid DT one. A simple second order modulator serves as an example to illustrate the application of lifting not only to an ideal but also to a non-ideal modulator covering typical non-idealities such as finite opamp gain, finite gain-bandwidth, excess loop delay and even jitter.

This paper deals with one of the most outstanding advantages of continuous-time sigma-delta modulators compared to their discrete-time counterparts: the implicit antialiasing feature. Although inherent in any continuous-time architecture, calculation methods and discussions have mostly dealt with single-stage modulators in the past. This contribution covers the calculation method and the discussion of the antialiasing feature of continuous-time multi-stage noise-shaping sigma-delta architectures. A theoretical model will be introduced and confirmed through simulation results. Thereby, it will be proven that usually all stages of a cascaded architecture are involved in the anti-aliasing behavior and hence that it is not solely determined by the first stage.

Charge balancing is a major concern in functional electrical stimulation, since any excess charge accumulation over time leads to electrolysis with electrode dissolution, gazing and tissue destruction. This paper presents an overview on recent advances in this field: passive as well as active charge balancing techniques will be presented concerning their advantages and drawbacks. For closed loop active charge balancers a stability analysis is presented

This paper presents a novel architecture for a highly efficient rectifier circuit. The rectifier can be fully integrated using a standard CMOS process without special process options. The needed dynamic bulk regulation transistors are inherent in the first stage. A full wave rectifier with only one threshold voltage drop and an efficiency of approximately 50% is realized. In combination with a low-power active diode the proposed rectifier shows nearly no voltage drop and the efficiency rises up to 90%.

A decaying pulse shape DAC architecture for continuous-time (CT) SigmaDelta modulators is introduced. The DAC reduces the clock jitter sensitivity while putting only moderate design constrains on the respective integrators. The impact of clock jitter on the entire SigmaDelta modulator is computed and verified by electrical and behavioral simulations. In order to illustrate also the low-power benefits, the required integrator gain-bandwidth is evaluated and the obtained results are compared with corresponding simulation results. The DAC is implemented in a 1.8V 0.18mum CMOS process operating at a sampling frequency of fS=200MHz. The effect of process corners, supply voltage and temperature (PVT) is illustrated. Finally, various design constrains are discussed

This paper presents the system and design of a retina stimulator with 232 electrodes in a 0.35mum HVCMOS technology. The requirements are outlined and the system architecture is explained. The stimulator provides more than plusmn15 V output swing, features full custom ESD protection at the electrodes and is fully testable. To prevent electrolysis through dc-currents, a new active charge balancer is implemented. Measurement results confirm the approach