This paper proposes a chip–PCB hybrid switched-capacitor (SC) physical unclonable function (PUF) to detect PCB-level attacks using only two, or even a single, sense IO. An on-chip capacitor array is employed to compensate for and balance the capacitances between the two sense IOs (or between one sense IO and one on-chip capacitor). The sense IOs then form a sense SC circuit, while two on-chip capacitors constitute a reference SC circuit to which a small threshold capacitor is further introduced. An unchanged relationship between the output voltages of the sense and reference SC circuits under variation of the threshold capacitor in the reference SC circuit indicates that the capacitance mismatch between the two sense IOs (or between a sense IO and an on-chip capacitor) exceeds a predefined threshold. This reflects a significant change in the capacitance of the sense IO, potentially caused by PCB-level desoldering, resoldering, or probing attacks. Furthermore, the two capacitors in the reference SC circuit are partitioned into multiple sub-capacitors to form multiple sub-reference SC circuits. Together with the sense SC circuit, these structures constitute multiple SC PUF units that generate PUF keys strongly correlated with the parasitic capacitance of the sense IOs. The proposed anti–PCB-level attack scheme is fabricated in a 180nm CMOS process for silicon verification. Measurement results demonstrate that the SC PUF output keys effectively reflect IO capacitance variations caused by PCB-level attacks, thereby providing reliable protection for the chip against such attacks.

The latch-styled sense amplifier (LSSA) is widely used to amplify the micro-output voltage of a physical unclonable function (PUF) due to its compact size and low cost. However, the offset in LSSA is large, and current methods for offset cancellation struggle to eliminate the offset caused by mismatches of the two input NMOS and two PMOS transistors while maintaining compatibility with both resistive and capacitive inputs. To address this issue, we store the offset introduced by the transistors in the two output capacitors and use two additional input capacitors to isolate the influence of the input signals’ DC voltage. Moreover, all circuits in the offset-canceled (OC) LSSA are constructed using MOS transistors with the minimum allowable length, allowing for the proposed OC LSSA to be easily realized using advanced FinFET processes and integrated into the chip through digital design flow. The proposed OC LSSA is integrated in a switched-capacitor (SC) PUF and fabricated using the 7 nm FinFET process, as well as the 28 nm and 180 nm standard CMOS processes. Test results verify the effectiveness of the offset cancellation method for the LSSA. The bit error rate (BER) across all working environments of the SC PUF using 7 nm, 28 nm, and 180 nm processes decreases from 21.98%, 14.10%, and 7.19% to 7.81%, 4.86%, and 1.88%, respectively, after applying the proposed offset cancellation LSSA to amplify its output voltage.

Conventional relaxation oscillators typically rely on reference circuits to generate switching threshold voltages or charging currents, resulting in increased chip area and power consumption. This article presents a high-precision relaxation oscillator that eliminates the need for reference circuits. A holding capacitor is charged through a timing resistor, and the switching threshold voltage is directly derived from the power supply using a resistor divider. Since both the charging speed and the switching threshold voltage scale with$V_{\!D\!D}$, their dependencies cancel each other out, resulting in an oscillation period determined solely by the time constant of the holding capacitor and timing resistor. Moreover, the tracking behavior of the switching threshold with respect to$V_{\!D\!D}$further reduces the sensitivity of the comparator delay to supply voltage variations. A dual-path charge–discharge scheme is also employed to eliminate frequency deviations caused by digital logic delays and capacitor discharge time. Fabricated in a 110-nm CMOS process, the oscillator operates at 24.5 MHz with an active area of 0.026 mm2. Measurement results indicate a power consumption of$160~\mu $W and a maximum frequency error of 1.88% across a temperature range from −55 °C to 125 °C, corresponding to a temperature coefficient of 140 ppm/°C. When$V_{\!D\!D}$increases from 3.0 to 3.6 V, the output frequency variation is 0.4%.

A design method is presented to protect the power switch from negative voltage at the input power supply due to the connecting or disconnecting the power line. To ensure proper power supply acquisition under positive input conditions and isolation under negative input conditions, a negative input isolation circuit is first used for the non-power circuit. Then, two protective NMOS transistors are used to pull the gate and substrate of the power NMOS transistor to the negative VIN to prevent leakage current in the power NMOS transistor. At the same time, two simple switches which conduct under positive VIN and cutoff under negative VIN are used to effectively turn off the two protective NMOS transistors, preventing them from affecting the normal multi-mode operation of the power switch during positive VIN. This circuit does not require an additional positive voltage power supply and does not introduce voltage drop, providing negative protection for all devices and circuits between VIN and GND as well as between VIN and VOUT. The proposed power switch is implemented using a 180 nm BCD process, and the test results show that the power switch can effectively mitigate −5 V negative voltage at the input power supply.

Most physical unclonable functions (PUFs) can be located by attackers and are vulnerable to various physical attacks due to their distinct image and circuit features. To address this vulnerability, this article proposes a featureless dual-mode latch-based (FDL) PUF that is concealed within the digital circuit. The FDL PUF is implemented using standard cells and a digital design flow. It is then randomly distributed among other standard digital cells within the chip to eliminate possible identification of image features. Moreover, the output key of the FDL PUF is randomly extracted, and the FDL PUF is then repurposed to store other intermediate variables of the security algorithm, effectively eliminating the circuit features. The proposed FDL PUF is integrated into a secure identity authentication chip fabricated using a standard 0.18-$\mu $m CMOS process. The feasibility of locating the FDL PUF units is evaluated using computer vision technologies, specifically YOLOv10 combined with OpenCV. Test results demonstrate that the number of suspected latch-based PUF units is approximately 15 times higher than the actual number of FDL PUF units for the test security chip, highlighting the significant challenge faced by attackers when attempting to locate the FDL PUF.