The authors introduce ILLIADS as a fast MOS timing and reliability simulator for very large digital MOS circuits. The use of the proposed general circuit primitive not only provides better accuracy but also significantly reduces the simulation time. The use of an analytic solution embedded in the simulation engine improves both the simulation speed and the accuracy. Postponing the waveform approximation process provides better waveform approximation even for non-fully-switching waveforms and glitches. The channel length modulation effect is captured accurately in fast timing simulation with only 10% of speedup tradeoff. It is also shown that ILLIADS manifests the charge sharing problem. The modified PWCTC algorithm, PWCTC-W, which handles circuits with feedback, is introduced and shown to be superior to the dynamic-windowing scheme. It also does not manifest the window-growing problem and is insensitive to the level of strongly concerned component (SCC) hierarchy. The use of this algorithm keeps the speedup of ILLIADS over SPICE for circuits with feedbacks at the same level as that for combinational circuits.>

The exact analytic transient solution is presented for a general MOS circuit primitive. In the circuit primitive, I-V characteristics of transistors are modeled by quadratic equations and node voltages by piecewise-linear waveforms. The proposed MOS circuit primitive, of which an inverter is a special case, is shown to be more suitable for switch level and fast timing simulations than the commonly used inverter. For circuit simulation of medium-size digital circuits containing a few hundred transistors, the application of this analytic solution has resulted in two to three orders of speed improvement over the conventional circuit simulator. The speed improvement factor is expected to grow with the circuit size. It is also shown that the exact transient solution of a macromodel which models the charge sharing can be obtained in the same way.>

By using a direct equation solver of a new MOS circuit primitive with piecewise-linear approximation of electrical waveforms, ILLIADS has been shown to be significantly superior to existing fast MOS timing simulators in both accuracy and speed.For simulation of medium-size digital circuits containing a few hundred transistors (n), ILLIADS has already achieved an O(n), about 3n or more, speedup over SPICE with error less than 3%.The sizes of circuits ILLIADS can handle is not limited by this method and the speedup is expected to grow with the circuit size.The possibility of generating false waveforms caused by merging of parallel transistors is reduced.A modified waveform relaxation algorithm is used to handle circuits with feedbacks as demonstrated through simulation of a ring oscillator and a updown counter.

A novel approach to incorporating the channel length modulation in a direct-equation solving fast timing simulator is presented along with a mixed event-driven and waveform relaxation algorithm to handle MOS VLSI circuits with feedback. Simulation speedup of 3N over SPICE-like simulators has been observed, where N is the number of transistors. The simulator is able to simulate circuits as large as 235000 transistors in 10 min real time. Also presented is a novel approach to fast hot-carrier reliability simulation. These methods make it possible to achieve accurate and fast hot-carrier reliability simulation of MOS circuits each with as many as hundreds of thousands of MOS transistors in a workstation environment.>