International audience

As technology scales, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise plays a greater role in sub-100nm technologies and creates signal integrity issues in the chip. It is vital to consider supply voltage noise effects (i) during design validation to apply sufficient guardbands to critical paths and (ii) during path delay test to ensure the performance and reliability of the chip. In this paper, a novel layout-aware pattern generation procedure for maximizing power supply noise effects on critical paths while considering local voltage drop impacts is proposed. The proposed pattern generation and validation flow is implemented on the ITC’99 b19 benchmark. Experimental results for both wire-bond and flip-chip packaging styles are presented in this paper. Results demonstrate that our proposed method is fast, significantly increases switching around the functionally testable critical paths, and induces large voltage drop on cells placed in the critical paths which results in increased path delay. The proposed method eliminates the very time consuming pattern validation phase that is practiced in industry.

Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shipped to the customers fault-free. However, at-speed tests have been known to create higher-than-average switching activity, which normally is not accounted for in the design of the power supply network. This potentially creates conditions for additional delay in the chip; causing it to fail during test. In this paper, we propose a pattern compaction technique that considers the layout and gate distribution when generating transition delay fault patterns. The technique focuses on evenly distributing switching activity generated by the patterns across the layout rather than allowing high switching activity to occur in a small area in the chip that could occur with conventional delay fault pattern generation. Due to the relationship between switching activity and IR-drop, the reduction of switching will prevent large IR-drop in high demand regions while still allowing a suitable amount of switching to occur elsewhere on the chip to prevent fault coverage loss. This even distribution of switching on the chip will also result in avoiding hot-spots.

The limitations of pattern generation tools are beginning to surface as parasitic coupling capacitance in high speed interconnects only worsens as the industry approaches sub-50 nm technologies. This can create a gap between the delay experienced on critical and long paths during test and the delay of the same paths in the field. In this paper, we propose a novel structural test pattern generation procedure that magnifies parasitic crosstalk effects on delay-sensitive paths by inducing switching on nearby nets which have been identified using the parasitic information of the layout. This will ensure timing closure on the targeted path is still met while also minimizing escape ratio and improving in the field reliability. Results of the proposed layout-aware approach demonstrate the ability of the proposed framework to significantly increase crosstalk around the targeted delay-sensitive paths.

Power distribution networks (PDNs) have been a vital part of modern designs. However, scaling technologies have increased the likelihood of defects in the PDN that may affect yield, escape, and reliability. Failure analysis is particularly difficult since there is no direct access to the PDN as there is to the design logic. We present a flow that generates transition-delay fault patterns to target open defects on the PDN. The flow identifies regions that could be susceptible to open defects and generates patterns that will exercise those regions to increase the likelihood of a timing failure should a defect exist in the PDN.

Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring these chips operate at the specified frequency. However, current industrially used X-filling (random-fill or compression) schemes tend to generate transition delay fault patterns with switching activity much higher than what would be seen during functional mode operation of the chip, potentially causing failures that would not occur in the field. In this paper, we present a low- switching transition delay fault pattern generation flow. The flow short-lists patterns based on high switching activity, which is determined by the fault lists of each pattern. Once those patterns with high switching are filtered, they will be replaced by low-switching patterns to recover any lost fault coverage. The proposed pattern generation flow works well with commercial tools and can easily be integrated into an industrial flow.

Traditionally, the only standard method of testing that has consistently provided high fault coverage has been scan test due to the high controllability and high observability this technique provides. The scan chains used in scan test not only allow test engineers to control and observe a chip, but these properties also allow the scan architecture to be used as a means to breach chip security. In this paper, we propose a technique, called Lock & Key, to neutralize the potential for scan-based side-channel attacks. It is very difficult to implement an all inclusive security strategy, but by knowing the attacker, a suitable strategy can be devised. The Lock & Key technique provides a flexible security strategy to modern designs without significant changes to scan test practices. Using this technique, the scan chains are divided into smaller subchains. With the inclusion of a test security controller, access to subchains are randomized when being accessed by an unauthorized user. Random access reduces repeatability and predictability making reverse engineering more difficult. Without proper authorization, an attacker would need to unveil several layers of security before gaining proper access to the scan chain in order to exploit it. The proposed Lock & Key technique is design independent while maintaining a relatively low area overhead.

Scan designs used for testing also provide an easily accessible port for hacking. In this paper, we present a new low-cost secure scan design that is effective against scan-based side-channel attacks. By integrating a test key into test vectors that are scanned into the chip, testing and accessing scan chains are guaranteed to be allowed only by an authorized user. Any attempt to use the scan chain without a verified test vector will result in a randomized output preventing potential side-channel attacks. The proposed technique has a negligible area overhead, has no negative impact on chip performance, and places several levels of security over the scan chain protecting it from potential attacks.