Digital Circuits are extremely vulnerable to reverse engineering which can reveal the design and functionality of an integrated circuit (IC) and expose valuable intellectual property (IP). A solution to this problem is to use different IC camouflaging techniques or gates to hinder the attacker’s ability to discover the functionality of the design. One type of camouflaged gate is the Threshold Voltage Defined (TVD) logic family. This gate type uses different threshold voltage transistors to disguise the functionality of the circuit. One of the drawbacks of the TVD logic family is that it is a synchronous logic family which makes it extremely vulnerable to Logic Laser State Imaging (LLSI) Attacks. This paper proposes using handshaking logic to create an asynchronous version of the TVD logic family to remove its vulnerability to LLSI attacks and to increase the speed of the TVD gates.

Physical attacks on secure devices can leak sensitive data and have significant consequences for individuals, companies, and governments. Today, much research is centered around understanding hardware weaknesses and vulnerabilities and, in turn, designing countermeasures to increase system security. One such countermeasure is the implementation of the camouflaging gate called PG-TVD (pass gate-based threshold voltage defined), which ensures protection against reverse engineering and sidechannel attacks. However, proper investigation is needed to determine if the countermeasure opens the door to other powerful attacks, such as laser fault injection (LFI) attacks. Identifying the vulnerability against this attack requires a proper assessment. As the first attempt to understand laser sensitivity in PG-TVD, we develop a workflow for assessing a circuit layout's sensitivity to LFI. We use this workflow to analyze the PG-TVD, giving the laser-sensitive areas. A deeper understanding of how to protect devices can be gained from this assessment to keep sensitive data secure. From the information obtained by our workflow, we also propose, design, and simulate a mitigation scheme that mitigates the laser sensitivity in PG-TVD logic cells by approximately 83%.

In this paper, parasitic resistors and capacitors which are created by via, a passive source of entropy, highly dependent on process variation is introduced to a latch based PUF. The parasitic capacitors and resistors are implemented by using meta12 to meta17 in 65nm TSMC technology node. Measurement results show without using any post stabilization, 1.29% instability, with 2000 repeated evaluations, is achieved. PUF evaluated over supply voltage and temperature from 0.8 V to 1.3 V and 0°C to 105°C, respectively. Instability of worst case varies from 3.1% to ~1.9% over supply voltage and from ~1.9% to ~2.2% over temperature. 103X distance ratio between inter and intra die hamming-distance is obtained.

This paper presents a new correlated level shifting (CLS) technique that relaxes the design criteria for the residue amplifier in pipelined successive approximation register (SAR) ADCs. Unlike prior techniques, this correlated level shifting technique does not load the residue amplifier during its initial estimation phase by sampling its output to generate an estimate for use in level-shifting. Instead, the estimate is generated by using the residue voltage stored on the SAR DAC to create a look-ahead path that charges the level-shifting and load capacitors before the start of amplification. The operation of the look-ahead CLS (LACLS) technique is described and its effect on key residue amplifier design criteria such as slew rate, linear output range, and dc gain is analyzed. Simulation results are provided to verify the technique in the context of a pipelined SAR ADC and a discussion is given on choosing an appropriate circuit-level implementation for the look-ahead path. Finally, the merits of look-ahead correlated level shifting are discussed and compared to other techniques.

This paper presents a novel physically unclonable function (PUF) for security authentication. Instead of using the variation of transistors or PDK provided passive components as entropy source, the parasitic resistance created between metal and via layers is used as the static entropy source. A symmetric bridge configuration consisted with the parasitic resistance creates the necessary voltage difference for comparison. An accurate backend incremental analog-to-digital converter (IADC) is implemented to convert the voltage difference into a digitized value. The operation of the IADC allows to achieve a good native instability. Two different types of layout structures are implemented to create the necessary parasitic resistance and compared. Fabricated in a 65nm process, the prototype PUF achieves a native instability and bit error rate of less than 1.45% and 0.12% with 5000 repeated evaluations. The proposed design shows 0.58%/0.1V and 0.53%/10°C bit error across the voltage and temperature range of 0.9 to 1.4V and 0°C to 85°C, respectively without any stabilization techniques. The distance ratio between intra-die and inter-die Hamming Distance is above$305\times $.

This paper presents a novel Self-Reset Transconductance Integrating Leakage Latch (STILL) which can be utilized as an ultra-low power method for sensor interfacing during the power saving or sleep modes of an IoT device. This simple circuit consists of 6 MOS transistors, 2 small capacitors, and a current starved NAND gate, resulting in a minimal footprint. Additionally, a 2nd-order temperature-compensated current reference is adopted to supply a sub-nanoampere current reference for the STILL, allowing stable operation and consistent power consumption regardless of temperature or process variations. To demonstrate the functionality of the STILL circuit and current reference, they are designed and fabricated in a 0.13μm CMOS process. The STILL circuit is shown to reliably detect an input signal change of 10mV at frequencies up to 1kHz. The power consumption of the STILL circuit and the current reference are measured to be 350pW and 2nW, respectively.

The effect of finite bandwidth of quantizers in continuous-time (CT) delta-sigma modulators (DSMs) is studied. It is shown that the finite quantizer-bandwidth in CTDSMs degrades the performance much more severely than it does in their discrete-time counterparts. It is demonstrated that CTDSMs with excess loop delay (ELD) compensation schemes require an even higher quantizer-bandwidth compared to ELD-free CTDSMs. Furthermore, it is shown that the required quantizer-bandwidth increases as the order and the out-of-band gain increases. Detailed mathematical analyses and simulation results are provided to show the effect of the finite quantizer-bandwidth.

A multi-path integrate-and-fire circuit is proposed as a new method of providing prosthesis sensory feedback in an effort to improve the response to dynamic stimuli. The proposed integrate and fire (I&F) utilizes adjustable thresholds and offsets on each path to provide two degrees of freedom to correctly match afferent firing frequencies. The proposed I&F was designed in TSMC 65 nm and its functionality was confirmed through simulations and comparing the response to afferent firing patterns expected for three sets of excitations.

This paper presents a design methodology to use time domain quantization noise information to further increase the order of the overall noise transfer function (NTF). Additional 2ndorder NTF can be achieved by using the time domain quantization noise information that is inherently available in the noise shaped integrating quantizer (NSIQ). The time domain quantization noise is delayed through a voltage controlled delay line (VCDL) and coupled to the NSIQ itself using only two coupling resistors. Therefore, no additional digital-to-analog converter (DAC) is required to both extract the quantization noise and couple to the loop, which is necessary in traditional voltage domain noise coupling scheme. Mathematical analyses and MATLAB simulation results are provided to prove the efficiency of the proposed scheme.

Counterfeit electronics impact the global economy and pose life-threatening risks to critical systems and infrastructure. Analog/mixed-signal (AMS) chips are the most widely reported counterfeit chip type, but existing countermeasures are impractical for detecting them. In this paper, we propose a method to detect recycled AMS counterfeits that exploits degradation of power supply rejection ratio (PSRR) in low drop out (LDO) regulators. Our zero cost approach does not require information about the component's design. Moreover, due to the ubiquity of LDOs, it may apply to active and legacy AMS system on chips (SoCs). To evaluate the feasibility and effectiveness of our method, we use an automated test setup to collect PSRR data from commercial off-the-shelf LDOs before and after aging. Machine learning algorithms ranging from unsupervised to supervised are applied to differentiate between aged (i.e., synthetically recycled) and new LDOs. Silicon results confirm that semi-supervised and supervised algorithms are effective even with LDOs used less than 10 days (for 65nm technology node).

In this paper, we present a thorough discussion and comparison between the single loop delta-sigma modulator (DMS), the multi-stage noise shaping (MASH) DSM and the sturdy MASH (SMASH) DSM focusing on circuit sensitivity and stability. It shows that the SMASH is least sensitive to the circuit non-idealities among all and its stability is in between the others.

A noise-cancelling sturdy multi-stage noise-shaping (NC-SMASH) structure that cancels first stage quantization error is proposed. Without any modification to existing analog blocks in the traditional sturdy MASH (SMASH) structure, adding digital noise-cancelling filters (NCFs) will cancel the first stage quantization error. This quantization error cancellation, unlike the traditional MASH structure, is less sensitive to analog loop filter matching and digital filters. This is because the leakage of the first stage quantization error is shaped by the overall noise transfer function (NTF) of the proposed NC-SMASH structure. Therefore, this technique allows using low gain opamps without signal-to-noise ratio degradation and reducing the number of the first stage quantization levels. Detailed Matlab simulation results are provided to prove the efficiency of the proposed modulator.

This paper presents a multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) using a back-end digital integrator in the first stage of the MASH DSM. By using the back-end digital integrator in the first stage, not only can the resolution of the first stage be improved, but the opamp dc gain requirement can also be relaxed. A new structure is proposed which avoids the need for quantization noise extraction digital-to-analog converters (DACs) when using the back-end digital integrator. Applying the proposed scheme, 3-level first stage quantizer will effectively operate as a 15 level quantizer, and accordingly the quantization noise leakage can be reduced. Detailed MATLAB simulation results and mathematical analysis are provided to prove the efficiency of the proposed structure.

This paper presents a new second-order temperature-compensated current reference which uses only one resistor. The behavior of the proposed bias circuit is analyzed in this paper, and the current reference circuits were designed and simulated in a 130 nm CMOS technology. From the simulation results, the proposed current reference achieved 327 ppm/°C in the temperature range of -30°C to +150°C, which is very wide. Its nominal current is 27 nA with a current variation of + 3% at a supply voltage of 1.2 V. Compared to a conventional first-order temperature-compensated current bias circuit designed for nano-amperes, the proposed current reference provides a current that is 4.7 times more stable over the temperature range of -30°C to +150°C. Also, the current drift from process corner variations deviates less than 3.7% from the simulation results.

This paper combines the benefits of the Sturdy-MASH delta-sigma modulator with the benefits of the noise-shaped integrating quantizer. By using the noise-shaped integrating quantizer, the first stage quantization error is directly extracted in time-domain without the need for any extra hardware. This removes the loading on the first loop filter, and allows accurate inter-stage gain scaling. The second loop output is also provided in a time-modulated pulse which operates a DAC at the front-end of the modulator. With the use of dual-DAC data weighted averaging, the mismatch between the front-end DACs is greatly suppressed. Detailed Matlab simulation results are provided to prove the efficiency of the proposed structure.

This paper presents a methodology to improve filtering in continuous time delta-sigma modulators (CTDSMs). A first order passive low pass filter is incorporated into the delta-sigma loop with a small modification of the existing active RC integrator configuration. The delay associated with the filter is compensated without any additional active components such as opamps. The proposed scheme provides an additional first order filtering to CTDSMs, resulting in an increased immunity to out-of-band blockers. Also, it relaxes the design complexity of the preceding filters. Detailed Cadence and Matlab simulations are provided to prove the operation of the proposed scheme.

In this paper, a new pulse width modulation (PWM) converter is proposed. This structure converts the analog input signal to a PWM waveform using only inverters/charge-pumps in combination with passive elements. Thus, the proposed PWM converter does not need any operational amplifier. The added feedback path current can be used to adjust the required duty-cycle of the PWM conversion based on the dynamic range of the input signal. The behavior of the proposed PWM converter is formulated and simulated in a 0.13μm CMOS technology. From the simulation results, the proposed PWM converter achieves 74dB linearity and draws only 1.0mA at 500MHz from 1.0V supply in a 0.13μm process.

A precise return-to-zero current steering DAC is presented. This architecture uses a scaled switched-capacitor replica and a comparator to integrate the current over time, resulting in an accurate pulse. Without significant increase in the pulse height, the generated pulse can have its minimal value at the end of the DAC phase, hence minimizing the clock jitter effect. The proposed DAC can be used in continuous-time delta-sigma modulators to achieve high accuracy even in presence of the clock jitter. Simulation results are provided to prove the efficiency of this structure.

A single-loop delta-sigma modulator based on path-coupling and double-sampling is proposed. This modulator employs a noise-shaped integrating quantizer which by itself increases the order of noise shaping by one. The integrating quantizer used in this structure holds its quantization error at the end of the evaluation phase, and hence this voltage is available in purely analog form and eliminates the need for extra DACs. This enables to utilize local path-coupling which adds another order of noise shaping. A third order example is provided and simulated to demonstrate the efficiency of this structure.

An extended version of sturdy MASH delta-sigma modulators is presented in this paper. Improved performance is achieved using in-band zero optimization. The challenges towards high order multi-loop modulators are discussed and a new multi-loop modulator is presented. This modulator benefits from a MASH architecture in the final loop to preserve stability, while the main loop benefits from relaxed circuit building blocks of the SMASH structure. Extensive simulation results are provided to prove the efficiency of this structure.

An enhanced version of Sturdy MASH (SMASH) (Maghari et al., 2006) delta-sigma modulator is proposed. This structure takes advantage of the well-known stability of the MASH structure while greatly reducing its sensitivity to imperfect circuit blocks. Furthermore, no digital noise cancellation filters are needed. Hence there is no matching requirement for the analog and digital paths. With the proposed enhancement in noise shaping, the first and second stage quantization noise experience different (thus mixed) orders of noise shaping, and the accuracy of this modulator is comparable of that of the MASH structure. Simulations results and mathematical analysis demonstrate the effectiveness of this structure.