Large multiplication is widely used in modern cryptography systems, multimedia and signal processing applications. This paper presents three pipelined large multiplier (PLM) design methods that use specialized multiplier logic provided in modern FPGA platforms. The presented design methods provide efficient usage of symmetric multiplier resources. Also, they can be used to map a large multiplier even on a small size FPGA. The syntheses results show that a pipelined 256-bit multiplier implemented in this paper uses 15 times less DSP slices on a Virtex 5 xc5vfx100t FPGA than a monolithic multiplier mapped on the same FPGA. The trade off is a three times reduction in the speed in this specific case.

Smith-Waterman algorithm is used to search bioinformatics databases. The systolic array implementations of this algorithm can search databases hundreds of times faster than software applications. The performances of the systolic Smith-Waterman implementations mainly depend on the number of cells they contain and the clock frequencies of the cells. This paper presents efficient cell designs for systolic Smith-Waterman implementations. The designs that use the presented cells and the recent reference designs are mapped on the same FPGA platform and compared by syntheses. Syntheses results show that the performance of the presented designs are 1.7 to 3.6 times higher than the reference designs.

This paper presents a general approach for designing array and tree integer multipliers with overflow detection. The overflow detection techniques are based on an analysis of the magnitudes of the input operands. The overflow detection circuits operate in parallel with a simplified multiplier to reduce the overall area and delay