External loopback testing is an industry standard test for serializer-deserializer (SERDES) interfaces, and it is used to test for at-speed defects in the analog transmission (TX) and reception (RX) buffers. The specific test involves sending pseudorandom bit sequence (PRBS) at high speed from the TX side, looping on the load-board and receiving on the RX side where the sequence is checked to calculate bit error rate (BER). To achieve parametric coverage on the buffers, it is required to have tester access at the SERDES pins. However, the on-board component populated for this tester access may lead to poor channel insertion and return loss due to reflections from these additional components. This, in turn, may lead to unacceptable BER at higher data rates. Consequently, it is a common practice to use one type of load-board for parametric/DC testing and another type for AC/at-speed testing. This paper describes a dedicated production load-board that is designed to achieve tester access on the SERDES pins using a resistor network. Using this load-board, external loopback could be operated successfully up to 20Gbps without sacrificing parametric test capability.

Finding the cause of yield and reliability issues has never been an easy task for the product and test engineer. The challenge continues to grow as processes add more steps and contain more complicated interactions, as designs are pushed to the limits of the process capabilities to meet their market requirements, as DPPM requirements continue to lower, and as test costs do not scale well. Test data has continued to become more critical in quickly resolving issues for fast ramps and maintenance of quality levels. However, the analysis methods are becoming more sophisticated and data intensive. This presentation will review some case studies, what was learned, and some observations.

Stringent quality requirements for integrated, heterogeneous systems have led designers and test engineers to mandate large sets of tests to be applied to these systems, which, in turn, have resulted in increased test cost. However, many of these tests are unnecessary (i.e., redundant), since their outcomes can be reliably predicted using results from other applied tests. A methodology for identifying the redundant tests of an integrated, heterogeneous system that has only binary pass-fail test data is described. This methodology uses decision trees, Boolean minimization, and satisfiability as core components. Feasibility is empirically demonstrated using test data from two commercially fabricated systems, namely, a high-speed serializer/deserializer (HSS) and a phase-locked loop (PLL). Our analysis of test data from > 38,000 HSS and > 22,000 PLL circuits show that 14 out of 40 HSS tests and 11 out of 36 PLL tests are redundant.

Integrated, heterogeneous systems are comprehensively tested to verify whether their performance specifications fall within some acceptable ranges. However, explicitly testing every manufactured instance against all of its specifications can be expensive due to the complex requirements for test setup, stimulus application, and response measurement. To reduce manufacturing test cost, we have developed a methodology that uses binary decision forests and several test-specific enhancements for identifying redundant tests of an integrated system. Feasibility is empirically demonstrated using test data from over 70 000 manufactured instances of an in-production microelectromechanical system accelerometer, and over 4 500 manufactured instances of an RF transceiver. Through our analysis, we have shown that the expensive cold-mechanical test of the accelerometer and nine out of the 22 RF tests of the transceiver are likely redundant.

In test compaction, the objective is to reduce cost of testing an integrated system by applying a subset of its specification-based tests. One approach for accomplishing this objective is to statistically learn a correlation function for the tests eliminated from a collection of systems that are fully tested (i.e., training data). Accuracy of this correlation function may degrade over the life span of an integrated system however. We describe an adaptive scheme that (1) uses stratified sampling to check the accuracy of a correlation function at various time instances and (2) re-learns a function when its accuracy dips below some tolerable threshold. This methodology is applied to test data from two in-production integrated systems, namely, an accelerometer and a phase-locked loop. Experiments that use over 200,000 real chips demonstrate that the difference between actual function accuracy and its estimate using stratified sampling is smaller than 2%. Moreover, our adaptive re-learning is able to improve the accuracy for one out of three accelerometer and one out of three PLL sampling instances where the function accuracy was unacceptable.

To mitigate fluctuations in the accuracy of test compaction, we propose to periodically verify this accuracy using stratified samples and adaptively update the models when it degrades below some acceptable limit. Application to an in-production accelerometer demonstrates the feasibility of this methodology.

We propose a methodology that employs boolean minimization and optimized test covering to identify redundant tests of a mixed-signal circuit from its pass-fail (binary) test data. This methodology is applied to two in-production circuits, a high-speed serializer/deserializer (HSS) and a phase-locked loop (PLL). Application of the methodology to over 38, 000 failing HSS circuits demonstrate that only 0.016% of them are mispredicted when three of nine high- voltage HSS tests are eliminated. Similarly, analysis of 22, 000 failing PLL circuits results in an error of 0.032% when 11 out of the 36 PLL tests are eliminated. Assuming 90% yield, these misprediction levels for the HSS and the PLL designs are equivalent to 16 and 32 DPM, respectively. The cost savings from eliminating the redundant tests in the HSS and the PLL designs at 90% yield are however estimated to be 21.9% and 30.9%, respectively.

Testing a non-digital integrated system against all of its specifications can be quite expensive due to the elaborate test application and measurement setup required. We propose to eliminate redundant tests by employing /spl epsi/-SVM based statistical learning. The application of the proposed methodology to an operational amplifier and a MEMS accelerometer reveal that redundant tests can be statistically identified from a complete set of specification-based tests, with negligible error. Specifically, after eliminating five of eleven specification-based tests for an operational amplifier, the defect escape and yield loss is small at 0.6% and 0.9%, respectively. For the accelerometer, defect escape of 0.2% and yield loss of 0.1% occurs when the hot and cold tests are eliminated. For the accelerometer, this level of compaction would reduce test cost by more than half.

Fault tuples have introduced a fault model independent methodology for digital circuit test analysis. However, the {0, 1, X} algebra currently used with fault tuples allows only one form of path sensitization. The sensitization options for fault tuples is enhanced based on a 5-value algebra. The 5-value algebra enables a more detailed test analysis through the selection of one of three types of sensitization. Simulation experiments performed using the ITC'99 benchmark circuits for transition and path delay faults reveal that faults can be simultaneously analyzed under different types of sensitization criteria with little increase in memory and CPU time.