The best-known IEEE standards in the test domain (JTAG 1149.1 and IJTAG 1687) have enabled the automation of the logic aspects of testing. However, the electrical aspects and the whole world of mixed-signal test are still left to ad-hoc solutions to be developed on the fly by design and test engineering teams. As a result, mixed-signal test consumes a disproportionate share of test time and development effort. The P1687.2 extension has set out to address analog test needs. Some of its concepts will be adopted by the next edition of the digital base standard IEEE 1687.This paper describes new methods for joining analog and digital test properties and behaviour with a consistent description, spanning from seemingly trivial aspects like bidirectionals and relays to co-existence with the full range of analog stimuli and measurements. True to the IJTAG mission of retargeting test procedures from IP to chip-level and beyond, mixed-signal test intent can be captured in a new standard language (PDL2) for a design block, which is instantiated multiple times, and retargeted across hierarchy levels, resolving the conflicts for limited resources like test pins and test buses.

Modern integrated circuits used in automotive, industrial, consumer, and IoT (Internet of Things) applications often have limited pin counts. Despite this, these devices can be complex, with significant digital and analog content. These features require rigorous testing to address the quality and reliability requirements of these applications. Because of their limited pin count, a TAP controller interface is often not an option or the TAP controller interface itself may not be an option for other reasons, such as die area. Further, the increasing number of IP based designs, along with the increasing availability of IP cores can result in an IP being integrated deep inside a design. Designers, DfT engineers, and test engineers are facing increasing challenges with the integration and testability of IP in their chips. They also have the task of having to test through interfaces that may change depending on the needs of the customers. IEEE P1687.1 is working on processes that will provide a means for automating communications through non-TAP interfaces, making these types of products ideally suited for the techniques currently under consideration for standardization. This paper, reviews the latest topics being discussed by the working group, including the framework for communicating through these interfaces. It discusses how proto buffers (protobufs) can be used to help bridge the gap between a host controller, like an ATE, and an IJTAG network. The approach leverages the concept of Remote Procedural Calls (RPCs) from the IT space and the integer bit vector (intbv) concept from myHDL to support communications through interfaces and between subroutines handling retargeting and handling control of the interface. A model is presented for evaluating the options and various criteria are reviewed with respect to the framework. The paper also explores debug concerns and potential security issues and how those can be addressed.

Display driver ICs traditionally feature high I/O counts to drive the many signals required for a high-resolution display. If LEDs are placed in a crosspoint matrix the driver IC only needs to drive the rows and the columns. But the recent advent of high-resolution micro-LEDs for adaptive automotive headlighting poses a new test challenge. The micro-LED chip is bonded on top of the silicon driver IC making connection via 20,000 I/Os, one per pixel. The driver IC becomes a backplane to the micro-LED array. Due to the I/O pitch of just$40\mu \mathrm{m}$and the sheer number of I/Os traditional probe card technologies become unviable. The paper describes a DfT concept that allows a self-test of the device on ATE, eliminating the need for any probing of the LED driver I/Os. Furthermore it delivers the necessary test infra-structure to prove the successful bonding between the driver IC and the micro-LED chip, allowing exact localization of assembly faults. During the mission life of the component the same DfT structures are used to monitor the health status of the headlight pixels, enabling the functional safety concept of the headlight system.

The increasing power supply demands of automotive SoCs that run ADAS applications require a high degree of configurability and trimmability of the Power Management Integrated Circuits (PMICs) that runs it. Thousands of configuration and trim bits are required that need non-volatile storage on-chip. The most trusted memories are based on floating gate (FG) technology. Automotive fitness of such non-volatile memory (NVM) is predominantly judged by its qualification status as per AEC-Q100. Whilst this is undeniably important, high-quality applications need test modes for every block, even the often “forgotten” digital decode and control logic, which in turn control test modes. A few examples show that without logic test even gross faults can escape the functional test of the NVM. The paper describes how a commercially successful OTP (One Time Programmable NVM) architecture with a proven track record in the consumer domain is enhanced to serve most demanding automotive applications in terms of test quality (coverage), reliability and functional safety (FuSa). It includes redundancy and stress modes for the memory array, reliability enhancements of the analog reference circuits, and digital test modes addressing any digital inside the entire OTP block.

The industry is moving forward with non-TAP, chip-level interfaces driving IEEE 1687-2014 networks. Recent literature not only describes such interfaces, like I2C and IEEE 1149.7 variants, but also demonstrates that such interfaces to IEEE 1687 are already proven in silicon. Common to those implementations is the need for "private" extensions of IEEE 1687 to make it support non-TAP interfaces. The goal of IEEE P1687.1 is to directly support non-TAP interfaces. In this work, we summarize the thought progression from IEEE 1687's data register callbacks to IEEE P1687.1's transfer function, which allows alignment with IEEE P2654, and possibly IEEE P1687.2.

Many modern devices have a very limited number of digital pins, yet they are often quite complicated internally. These ICs can't afford the luxury of a traditional JTAG TAP controller and the associated 4 or 5 extra pins. Nonetheless, these devices often contain significant digital and analog content. This complexity makes testing very challenging. Moreover, IP-based design often results in having an instrument buried deep inside a device, the access of which requires transitioning through multiple interfaces and controllers. This is exactly the situation DfT and test engineers face when designing and implementing tests for embedded IP. Techniques proposed for IEEE P1687.1 enable an automated mechanism for retargeting tests through a variety of non-TAP interfaces. This makes these products ideal candidates for IJTAG and IJTAG.1 test strategies. In this paper, we focus on demonstrating how on-chip test functions and IP can be successfully controlled and observed through non-TAP interfaces by controlling data flow using RVF (Relocatable Vector Format) and callbacks. This unique and novel approach ensures tool interoperability and allows tools to model interfaces in the same way, without requiring special descriptions for each one. The paper proposes an automated tool flow for retargeting the tests and provides example implementations on several specialized designs including I2C, an In-System TAP, IEEE 1149.7like interface, and a security block.

IJTAG (IEEE 1687) has proven to successfully address the challenge of test integration for “digital instruments” in digital systems on chip (SoCs). Yet, beyond SoCs, mixed signal IP presents an even bigger obstacle. This is particularly true for so-called Big-A/little-d chips, which have a significant number of analog IP blocks whose integration makes meeting fast test development cycle time requirements, from silicon to test program readiness, a challenge. Also, these chips rarely include a JTAG TAP for access to test data registers (TDRs) on scan chains. Instead, they have very simple serial interfaces, like $I^{2}C$ or SPI, and these are the only form of communication with the system and, consequently, with the ATE. This paper demonstrates the principles of test generation for a Power Management Integrated Circuit (PMIC) using the Procedure Description Language (PDL) of the P1687.2 standard. The authors show how a test procedure for a medium complexity analog block, an LDO (Low Drop Out regulator) can be retargeted and transformed to the chip top level and from there to the ATE test programs. The typical test infrastructure of the PMIC is modelled in ICL, the InterConnect Language of the IEEE standards 1687, P1687.1 and P1687.2. In addition, the employment of the P1687.1 callbacks enables transparent access of test registers via transformations through the serial communication interface.

The IEEE 1687-2014 standard introduced the concept of portable, retargetable tests for digital circuits and taught how to apply them via a JTAG Test Access Port. Two follow-on standardization efforts address the topics of portable, retargetable analog tests (IEEE P1687.2) and applying analog or digital tests via non-TAP interfaces (IEEE P1687.1). IEEE P2427 complements these efforts by defining how to measure and report coverage of analog tests. This session will use a running example to show how all three initiatives play together.

There is a growing demand for low-cost and effective test solutions to support state-of-the-art analog and mixed-signal systems that are continuously increasing in complexity and functionality, while decreasing in product cost. This innovative practice session highlights various aspects of design for test (DfT) in high-complexity, analog-dominated systems with three talks that focus on: DfT in power management integrated circuits (ICs), an alternative testing method to analog test bus, and pre-silicon built-in self-test (BIST) verification, where BIST is used to monitor complex mixed-signal systems. These talks will be given by industry experts from Dialog Semiconductor, Xilinx, and Texas Instruments.

Many analog and mixed signal devices have very few or no digital pins. In spite of this, these products can be highly complex internally, including significant digital content. They may contain various sensors and control circuitry, which react to a variety of conditions to control the power profile of the part and its environment. These factors can make these devices very challenging to test. They require complex circuitry, comprising digital control for setting test modes (stimulus) and for enabling observation features (response); these features are needed for each of the different product functions in order to characterize and screen them. For many applications, dedicated test pins are unacceptable because of manufacturing costs. Reducing the number of pins means fewer ATE instruments are required and the overall die and package footprint is minimized. Additionally, some analog and mixed signal devices may not have any digital IO functionality at all. And, adding digital capability at the IO for test purposes may not be an option. Further, for clocking during debug and during test entry, relying on internal oscillators may not be a good choice. The paper presents a unique one-pin input, for purposes of test that can carry a P1687.1-like protocol. It will show how the single-pin interface was implemented in silicon, including actual test results. The approach presented demonstrates how a single analog input can be used to provide clock and data information on a single pin.

Economic testing of small devices like LCD drivers is a real challenge. In this paper we describe an approach where a production tester is extended by a memory test engine (MTE). This MTE, which consists of hardware and software components allows testing the LCD driver memory at speed, allowing at the same time the concurrent execution of other tests. It is fully integrated into the tester. The MTE leads to a significant increase of memory test quality and at the same time to a significant reduction of the test time. The test time reduction that was achieved by executing the memory test in parallel to other analog tests lead to the test cost reduction, which was the impetus for developing the MTE

The huge code base of mixed-signal test programs is a significant challenge for the code generation productivity and for maintaining code quality which inherently translates into outgoing quality. This paper presents how the adoption of software engineering methods can address these challenges