Brute-force simulation approaches to estimating serial-link bit-error rates (BERs) become computationally intractable for the case when BERs are low and the interconnect electrical response is slow enough to generate intersymbol interference that spans dozens of bit periods. Electrical-level statistical simulation approaches based on superposing pulse responses were developed to address this problem, but such pulse-based methods have difficulty analyzing jitter and rise/fall asymmetry. In this paper we present a superposing-edge approach for statistical simulation, as edge-based methods handle rise/fall asymmetry and jitter in straightforward way. We also resolve a key problem in using edge-based approaches, that edges are always correlated, by deriving an efficient inductive approach for propagating the edge correlations. Examples are presented demonstrating the edge-based method's accuracy and effectiveness in analyzing combinations of uniform, Gaussian, and periodic distributed random jitter.

In this paper, we describe an approach for generating accurate geometrically parameterized integrated circuit interconnect models that are efficient enough for use in interconnect synthesis. The model-generation approach presented is automatic, and is based on a multiparameter moment matching model-reduction algorithm. A moment-matching theorem proof for the algorithm is derived, as well as a complexity analysis for the model-order growth. The effectiveness of the technique is tested using a capacitance extraction example, where the plate spacing is considered as the geometric parameter, and a multiline bus example, where both wire spacing and wire width are considered as geometric parameters. Experimental results demonstrate that the generated models accurately predict capacitance values for the capacitor example, and both delay and cross-talk effects over a reasonably wide range of spacing and width variation for the multiline bus example.

In this paper we describe an approach for generating geometrically-parameterized integrated-circuit interconnect models that are efficient enough for use in interconnect synthesis. The model generation approach presented is automatic, and is based on a multi-parameter model-reduction algorithm. The effectiveness of the technique is tested using a multi-line bus example, where both wire spacing and wire width are considered as geometric parameters. Experimental results demonstrate that the generated models accurately predict both delay and cross-talk effects over a wide range of spacing and width variation.