No-fault-founds (NFFs) threaten the dependability of highly dependable systems in avionic and car industries. Moreover, they drastically increase the test and maintenance costs. One of the main causes of NFFs is intermittent resistive faults (IRFs). IRFs mostly occur due to unstable and marginal interconnections. This paper proposes a new periodic testing method to detect IRFs in interconnections at the chip and the board level. The proposed method is based on on-chip embedded test instruments (ETIs), which are scalable, fully digital, and With a low hardware cost. As a case study, a network-on-chip (NoC) infrastructure with a mesh topology has been utilised. The implementation of the testing method requires a small chip area and power consumption overheads being 3% and 2.5%, respectively. In this paper, first, IRF detection at the chip level has been investigated using simulation-based fault injections in selected interconnections of the NoC. Then, the effectiveness of the proposed method at the board level has been verified by hardware-based fault injections as well as thermal cycling experiments on actual solder joints. The experimental results demonstrated that the on-chip ETIs can be reused effectively to detect IRFs at the board level.

The usage of embedded instruments (EIs) in a processor core to address dependability challenges of modern-day Multi-Processor System-on-Chip (MP-SoC) has been studied in literature extensively. Data from these EIs can be used in applications like end-of-lifetime (EOL) predictions. However, inaccuracies present in the data from these EIs, due to their self-aging and resolution limitations during digitization, can lead to an inaccurate EOL assessment. In this paper, it is presented that in the presence of such inaccuracies from EIs as well as correlation between EIs, principal component analysis (PCA) based data-fusion approach for determining the EOL of selected critical paths provided overall better EOL predictions as compared to EOL predictions based on standalone EIs. Verification was performed with a commercial software-based EOL predictor tool ARULE running on a personal computer. Moreover, the presented results on the computational requirements for the presented data-fusion approach showed little overhead in terms of memory, execution time and energy requirements.

The dependability of highly dependable systems relies on the reliability of its components and interconnections. One of the most challenging faults that threatens the reliability of interconnections in a system are intermittent resistive faults (IRFs). They may occur randomly in time, duration and amplitude in every interconnection. The occurrence rate can vary from a few nanoseconds to months. As a result, evoking and detecting such faults is a major challenge. In this paper, IRF detection at the chip level has been tackled by utilising a fully digital insitu IRF monitor. This paper introduces a new algorithm for inserting IRF monitors in a design. The goal of this algorithm is to minimise the number of IRF monitors while providing a high fault coverage for IRFs. The algorithm has been validated using software-based fault injection. The simulation results show that the proposed algorithm improves the IRF coverage at the chip level at the cost of a small area and power-consumption overhead.

Recently, the usage of on-chip embedded instruments (EIs) to ensure dependable safety-critical systems is becoming inevitable. These EIs can help to provide self-awareness, and their feedback can be used in different applications, e.g. end-of-lifetime (EOL) predictions. However, inaccuracies present in data from these EIs, due to their resolution limitations, self-aging and quantization errors during digitization, can lead to an inaccurate EOL assessment. To address this challenge, a machine learning-based system-level approach for determining the EOL of a many-processor system-on-chip (MPSoC) is discussed. It is based on the synchronous data capture of different IJTAG compatible EIs. To this end, two different data fusion techniques have been used for enhancing the accuracy of lifetime prognostics of multiple EIs; use is made of Independent Component Analysis (ICA) and the auto-encoder (AE). Different combinations of fused EIs (based on ICA and AE) along with standalone EIs for four different critical paths (CPs) have been investigated. For lifetime prediction based on different EIs/fused EIs, a data-driven degradation model was derived, and nonlinear regression has been employed for parameter estimation. Results show that data fusion of different EIs helps in obtaining better estimation of the EOL as compared to using a standalone EI.

Nowadays, a rapid introduction of very complex nanometer Many-Processor Systems-on-Chip in safety-critical applications is taking place. Unfortunately, it pairs with an unacceptable decrease in dependability of these complex nanosystems if no additional countermeasures are taken. To address this challenge, a promising approach is presented in this paper that uses a set of IJTAG compatible embedded instruments (EIs), in and around a processor cores to monitor their present health status. Data from these EIs is collected and fused for lifetime prognostics and hence dependability. For the EIs data fusion, use is made of principal component analysis (PCA) technique. For lifetime prediction based on different EIs, power-law degradation model was used.

The deployment of embedded instruments (EI) for online monitoring of a cyber-physical system-on-chip (CPSoC) for safety-critical applications has started getting more attention in recent years. Among these different types of EIs, the timing embedded instruments (to observe timing violations) are widely adopted to ensure a dependable operation during its operational lifetime. However, infield temperature variations together with self-aging of the timing EI affects its output, making it less reliable. This paper presents an IJTAG compatible, in-situ slack-delay timing embedded instrument to monitor critical paths in a CPSoC. The main contribution of the proposed design is the infield, online calibration mechanism. It enables the EI to self-calibrate for relatively fast-changing environmental variations like temperature, as well as slow changing variations like aging. The design has been implemented using a TSMC 40nm LP standard cell library. Simulation results show an average resolution of 13ps with a monitoring window of 13ps-416ps, which is sufficient to monitor the CPSoC for small timing margins. To further demonstrate the IJTAG compatibility, an FPGA implementation of the proposed design is also presented.

The IEEE 1687 standard defines a standardized mechanism for the off-chip access of embedded instruments. A subset of these instruments are also used for maintaining the reliability and functional safety of the chip during its lifetime. For example, temperature sensors, voltage monitors and Built-In-Self-Test engines. In this paper, we present a novel on-chip controller for IEEE 1687 networks which can execute instrument procedures documented in the IEEE 1687 PDL language. These procedures are incorporated within the reliability and functional safety embedded software that uses the measurements data of the instruments. The controller includes an efficient structural model of the IEEE 1687 network and can perform on-chip pattern retargeting on arbitrary networks. In addition, it can perform localization of instrument interrupts that are propagated via multi-mode IEEE 1687 networks.

Electronic design automation tools used for Design-For-Test infrastructure insertion have often relied on test standards (e.g. IEEE 1149.1, 1500 and 1687) as a structured methodology for IC test access, which consequently reduce the design cost for DFT. The IEEE 1687 standard introduces an efficient methodology for the off-chip access of the increasing number of embedded instruments that are used for test, debug and other purposes. A subset of these instruments is also used for Reliability and functional Safety (RaS) management, while accessing them via an on-chip manager. In this paper, we present a design automation framework for the RaS management of System-on-Chips using embedded instruments, by utilizing the IEEE 1687 standard as the key enabler of this automation. The framework enables the on-chip execution of cross-layer RaS procedures by the automatic generation of a dedicated design layer for the procedures execution. The framework utilizes the IEEE 1687-defined PDL language and the pattern retargeting process for enabling a programming model for developing the RaS procedures with no regard to the instruments access procedures and their physical locations, which consequently reduce the development time of RaS procedures and enable their scalability and reusability, and hence their automation.

The IEEE 1687 standard introduced a large design space of compliant networks for accessing embedded instruments. Such networks could grow in their structural complexity and inter-component temporal dependencies. Scan pattern retargeting is defined as the procedure of translating an instrument-level pattern to several network-level ones. Pattern retargeting could become computationally intensive with the increase of structural and temporal dependencies. Structured pattern retargeting was previously introduced as a formal and light-weight pattern retargeting methodology for arbitrary IEEE 1687 networks. In this work, we present a dedicated structured retargeting method for hierarchical IEEE 1687 networks. The proposed method significantly reduces the retargeting time for pure hierarchical networks compared to the general one, while resulting in the same network access time. The retargeting time is of a special importance in the case of on-chip retargeting, which is used for on-line monitoring using IEEE 1687 networks.

interconnection reliability issues threat the dependability of highly dependable systems. One of the most challenging interconnection-induced reliability threats is intermittent resistive faults (IRFs). They may occur randomly in time, duration and amplitude in every interconnection. The occurrence rate can vary from a few nanoseconds to months. As a result, evoking and detecting such faults is a major challenge. In this paper, IRF detection at the board level has been investigated by introducing a new digital IRF monitor. This monitor has been validated by using hardware-based fault injection. Two widely used on-board transmission protocols —UART and SPI —have been used as case studies. In addition, one fault management framework —based on the IJTAG standard —has been implemented to collect and characterize information from the monitors. The experimental results show that the proposed monitor is effective in detecting IRFs at the board level.

This is an overview paper that motivates and describes performed work done in the European Commission funded research project BASTION, which focuses on two critical problems of modern electronics: the No-Fault-Found (NFF) and CMOS ageing. New defect classes contributing to NFF have been identified, including timing related faults (TRF) at board level and intermittent resistive faults (IRF) at IC level. BASTION has addressed the mechanisms of ageing and developed several techniques to improve the longevity of electronic products. Embedded Instrumentation, monitors, and IEEE 1687 standard for reconfigurable scan networks (RSN) are seen as an important leverage that helped mitigating the impact of the above listed problems by facilitating a low-latency, scalable online system health monitoring and error localization infrastructure as well as integration of all heterogeneous technologies into a homogeneous demonstration platform. This paper helps the reader to get a general overview of the work performed and provides a collection of references to publications where the respective research results are described in detail.

Electronic systems are replacing mechanical parts to improve the safety and performance of the cars. However, the electronic components should be dependable, meaning they should be trusted to work properly over time. AMR sensors are widely used in automotive for angle measurements. Nevertheless, they are affected by performance degradation and catastrophic faults. Both should be handled to guarantee the correct operation of the sensor over time. This paper proposed two modules, fault-tolerant, and self-calibration. Results show they allow to improve the dependability of the sensor.

A cost-efficient framework for executing life-time dependability procedures is presented in this paper. The proposed framework relies on distributed sensors and actuators (embedded instruments) for self-awareness and adaptation, where the IEEE 1687 standard (iJTAG) is utilized for the dependability communications and the on-chip access of the instruments.

In safety-critical systems, many-processor Systems-on-Chip are being increasingly employed. An example is an imminent collision detection System-on-Chip for cars. Such a system requires zero downtime and a very high reliability despite aging issues under harsh environmental conditions. By monitoring the health status of processor cores and other IPs, and taking appropriate counteractions if required, we accomplished this goal via IJTAG compatible embedded instruments. This paper shows the design of the required IJTAG network, and a number of new IJTAG-compatible embedded instruments like slack-delay, power-supply current IDDT and Intermittent Resistive Fault monitors. In addition, we discuss their numbers and optimal locations in a processor core and provide a PDL description for one of our embedded instruments. In the case of for instance a four-processor implementation, requiring only two for actual data processing, the lifetime can increase by a factor of roughly three.

The increasing replacement of mechanical parts by x-by-wire systems in automotive applications allows improving driver safety. These systems demand highly dependable sensors that ensure their functionality despite the harsh operating conditions. This means that the sensors should be capable of working continuously despite catastrophic faults and keeping the performance over time. An anisotropic magnetoresistance (AMR) sensor is a magnetic sensor commonly used for angle measurements in cars. It is affected by catastrophic faults and performance degradation due to undesired parameters included at the sensor outputs. Until now, physical redundancy is often used to handle catastrophic faults. For the performance, compensation factors for the undesired parameter, such as offset voltage, are estimated at the start of the sensor life. Although the undesired parameters drift due to aging effects, the sensor performance remains within the allowed tolerant band. However, this tolerant band will decrease in the future because the dependability requirements are continuously increasing. Therefore, it is necessary to consider strategies to guarantee the sensor performance over time. This paper proposes a system to improve the sensor dependability using analytical redundancy for catastrophic faults but also with self-x properties to maintain the sensor performance over time. Results indicate a dependability improvement in terms of reliability, with a reduction of 50% in the rate of uncovered failures. The safety requirement ASIL level D is satisfied, and with regard to maintainability, the sensor performance is maintained over time.

In safety-critical cyber-physical systems, analog front-ends combined with many-processors are being increasingly employed. An example is an imminent collision detection chip for cars. Such a complex system requires zero downtime and a very high dependability despite aging issues under harsh environmental conditions. By on-line monitoring the health status of the processor cores and taking appropriate counteractions if required, we have accomplished this goal in the past via IJTAG compatible embedded instruments and appropriate embedded software. This paper extends this approach to the analog / mixed-signal frontends of these systems, thereby creating a new uniform approach in design & test methodology, as well as a streamlined fault management. An IJTAG-compatible voltage monitor is introduced, for measuring aging-generated offset in OpAmps and SAR ADCs, as well as a delay-monitoring embedded instrument for detecting timing issues in ADCs. In addition, two-stage counter measures, like digitized recalibration and subsequent replacement, are presented to increase the lifetime by factors of the analog front-end of Cyber-Physical Systems-on-Chips.

The IEEE 1687 (iJTAG) standard introduces an efficient access network based on reconfigurable scan, for accessing the increasing number of embedded instruments. Pattern retargeting is defined as the process of translating an instrument pattern to several network-level scan vectors. In this paper, an efficient structured methodology is presented for performing dynamic pattern retargeting. Dynamic retargeting is required in case of runtime access of the iJTAG networks, for example in debugging or reliability management. The presented methodology enables faster pattern generation as compared to previous search-based methods which is necessary for runtime access. This methodology could be used in a lightweight iJTAG debugger or in a software-based on-chip iJTAG controller.

This paper describes the usage of IDDX monitors, which provide (periodic) data to be employed for predicting the remaining life-time of processor cores in homogeneous multi-processor SoCs during their lifetime. This forms the basis of self-repair with no down time for these SoCs and dramatically improving their dependability. This goal is accomplished by combining the optimally designed health monitors, such as delay and current monitors, to provide non-redundant data. Nowadays these can be implemented as embedded instruments which are IJATG compatible. Accelerated stress tests have been carried out using a set of processor cores in combination with a number of health monitors providing historic data. These results form the basis of a remaining lifetime model for delay (clock frequency), where the coefficients are determined by a genetic algorithm. After final test of a SoC these coefficients are periodically updated in an embedded processor during lifetime by the health monitors. In the case of seriously degrading cores, counteractions are automatically taken, like core isolation and (e.g. spare) replacement. Use is made of advanced run-time mapping software. The result is a zero mean down-time SoC with 40% reliability improvement in our 9 processor-core SoC.

The required dependability of integrated CMOS systems has to be continuously increased because nowadays many applications are safety-critical. Having a good knowledge of potential realistic faults plays an important role in this case. The most difficult and expensive category of faults that can occur are the no-faults found (NFF). We have investigated the influence of intermittent resistive faults (IRF), an NFF resulting from e.g. cracks in ball-grid array-to-board interconnections and on-chip interconnections. Previous circuit simulations from us have indicated the potential effect of IRFs on the behavior of analogue as well as simple digital CMOS circuits. In this paper, a hardware IRF generator is presented to accelerate the IRF fault injection process. As a case study, a digital CMOS UART is selected and experimental results for software and hardware-based fault injections are provided. The experimental results demonstrate that the IRF fault injection can be accelerated by 7 orders of magnitude.

IEEE 1687 (iJTAG) standard introduces a methodology for accessing the increasing number of embedded instruments found in modern System-on-Chips. Retargeting is defined by iJTAG as the procedure of translating instrument-level patterns to system-level scan vectors for a certain network organization. The analysis and the design of an on-chip retargeting engine is presented in this paper. Performing retargeting on-chip enables the execution of life-time dependability procedures using embedded instruments. The proposed engine is capable of retargeting instruments' patterns using an optimized model of the network, which is extracted by resolving the dependencies between the data registers of the instruments and the network-state registers.

CPS, that consist of a cyber part – a computing system – and a physical part – the system in the physical environment – as well as the respective interfaces between those parts, are omnipresent in our daily lives. The application in the physical environment drives the overall requirements that must be respected when designing the computing system. Here, reliability is a core aspect where some of the most pressing design challenges are: monitoring failures throughout the computing system, determining the impact of failures on the application constraints, and ensuring correctness of the computing system with respect to application-driven requirements rooted in the physical environment. This paper provides an overview of techniques discussed in the special session to tackle these challenges throughout the stack of layers of the computing system while tightly coupling the design methodology to the physical requirements.

Anisotropic Magnetoresistance (AMR) sensors are often used for angle measurements. The sensor outputs consist of two sinusoidal signals that show undesired characteristics as offset voltage, amplitude imbalance and harmonics, which affect the angle measurements. These parameters change due to aging effects, but until now it is considered that these variations do not affect the sensor accuracy. The largest sources of angle error are compensated at the start of the sensor life but they are not monitored during its lifetime. However, the accuracy requirements are increasing and in the future, it will be necessary to verify that the sensor satisfies the accuracy despite aging. This research proposes different equations that are useful to monitor online the maximum angle error due to different sources. Based on this information it is possible to take action in order to guaranty the accuracy during the entire sensor lifetime.

Anisotropic Magnetoresistance (AMR) sensors are magnetic sensors often used for angle measurements. The sensor outputs should be two perfect sinusoidal signals that depend on the angle to be measured. However due to non-ideal properties of the sensor, the actual outputs include undesired parameters as offset voltage, amplitude imbalance and harmonics. All of them generate errors in the angle calculation. Offset voltage and amplitude imbalance are the first and second largest sources of angle errors for which until now are the mainly compensated. The required compensation factors are usually estimated at the start of the sensor life and not updated during its lifetime. Although the sources of angle errors show variations due to wearing and aging effects, so far it is considered that these variations are not significant to affect the sensor accuracy. However, this will change in the future, especially in safety-critical applications that will demand higher accuracy. Then it will be necessary to update the compensation factors during the sensor lifetime. This paper proposes an online compensation method to reduce the offset voltage, the amplitude imbalance and hence the angle error in AMR sensors. It was verified using simulated data as well as real measurements, showing a good performance in all the cases. Unlike most of the compensation methods proposed until now, our method is suitable to be used during the sensor lifetime.

Thermal phenomena occurring along test execution at the final stages of the manufacturing flow are considered as a significant issue for several reasons, including dramatic effects like circuit damage that is leading to yield loss. This paper tries to redeem those bad guys in order to exploit them to improve the test quality, reducing the overall test cost without affecting the yield.

A major threat in extremely dependable high-end process node integrated systems in e.g. Avionics are no failures found (NFF). One category of NFFs is the intermittent resistive fault, often originating from bad (e.g. Via or TSV-based) interconnections. This paper will show the impact of these faults on the behavior of a digital CMOS circuit via simulation. As the occurrence rate of this kind of defects can take e.g. One month, while the duration of the defect can be as short as 50 nanoseconds, to evoke and detect these faults is a huge scientific challenge. An on-chip data logging system with time stamp and stored environmental conditions, along with the detection, will drastically improve the task of maintenance of avionics and reduce the current high debugging costs.

In this paper, functional unit-based IDDT testing has been applied for a 90nm VLIW processor to monitor its aging degradation. This technique can provide health data for reliability evaluation as used in e.g. prognostic software for lifetime prediction. The test-program development based on the architecture of a single DSP processor, as well as implementation of an accelerated test (AT) is investigated and IDDT measurement results are evaluated. It is found that decrements of peak IDDT values of crucial functional units inside the processor characterize the power-law degradation with the aging time. This is in coherence with the aging behaviour of (PMOS) transistors caused by Negative-Bias-Temperature-Instability (NBTI), thereby validating the feasibility of this technique in monitoring target-process aging degradation.

Traditional reliability tests use complicated equipment, like probe stations and semiconductor parameter analyzers, to measure changes in transistors' threshold voltages, which are both expensive and time consuming. This paper provides an idea to test the threshold voltage with existing low-to-moderate accuracy ADCs and DACs inside SoCs. To avoid the low-accuracy limitation of measurement results, a new MOS model for the nano-meter MOS transistor drain current is proposed. This model only uses six parameters and is valid for all regimes, being the sub-threshold/weak-inversion, moderate-inversion, strong-inversion and linear regime. Measurement results from 90nm transistors and simulation results from 65nm BSIM4.6 models are used to validate the new model. Finally, an on-chip threshold test for reliability purpose is proposed and long-time stress measurement for 90nm PMOS transistors are shown.

Recently, several application areas in the test domain (e.g., burn-in and aging monitoring) started to require suitable input stimuli, able to maximize the switching activity of a certain module for a certain period of time. If the module is part of a processor, this turns into identifying a suitable sequence of instructions, able to maximize the switching activity. This paper proposes a method to attack this problem, and reports some experimental results gathered on a MIPS-like pipelined processor.

Anisotropic Magnetoresistance angle sensors are widely used in automotive applications considered to be safety-critical applications. Therefore dependability is an important requirement and fault-tolerant strategies must be used to guarantee the correct operation of the sensors even in case of failures. AMR sensors are configured with two Wheatstones bridges where catastrophic (hard) as well as parametric faults can ocurr. Catastrophic faults are mainly related to the conditions of the bridge resistances. If a hard fault occurs at any of the resistances, the sensor must be taken out of operation because the angle can not longer be reliably computed. Previous proposed fault-tolerant systems are based on physical redundancy with hardware duplication, which usually implies higher production cost and can be restricted by the mechanical construction of the sensor. However the proposed fault-tolerant system is based on analytical redundancy to obtain the required voltages to calculate the angle. Results indicate the fault-tolerant system can handle catastrophic fault at any of the bridge resistances, which is especially useful in safety-critical applications. Future research will be focused on parametric faults.

Analog and mixed-signal IPs are increasingly required to use digital fabrication technologies and are deeply embedded into system-on-chips (SoC). These developments append more requirements and challenges on analog testing methodologies. Traditional analog testing methods suffer from less accessibility and control with regard to these embedded analog circuits in SoCs. As an alternative, an embedded instrument for analog OpAmp IP tests is proposed in this paper. It can provide the exact gain and offset values of OpAmps instead of only pass/fail result. What's more, it is an non-invasive monitor and can work online without isolating the DUT Opamp from its surrounding feedback networks. Nor does it require accurate test stimulations. In addition, the monitor can remove its own offsets without additional complex self-calibration circuits. All self-calibrations are completed in the digital domain after each measurement in real time. Therefore it is also suitable for aging-sensitive applications, in which the monitor may suffer from aging mechanisms and has additional offset drifts as well. The monitor measurement range for offset is from 0.2mV to 70mV, and for gain it is from 0dB to 40dB. The error for offset measurements can be 10% of the measurement value with plus/minus 0.1mV, and -2.5dB for gain measurements.

In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.

An embedded health-monitoring infrastructure for a highly reliable MP-SoC for data-streaming systems is presented. Different from the traditional approach of a dependable design, our infrastructure is based on life-time prognostics from health-monitoring sensors that are embedded near the target processor. This enables the preventive repair by spare parts or priority ranking of tasks among processors. Focus of this paper is mainly the health-monitoring scheme and the sensor structure with simulation results.

This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic has been elaborated with a fast recovery mechanism to isolate the fault-free functional units and re-execute the erroneous instruction. These techniques have been implemented on a DSP processor in order to assess the achieved fault-tolerance versus the imposed overheads.

Reliability of electronic systems has been thoroughly investigated in literature and a number of analytical approaches at the design stage are already available via examination of the circuit-level reliability effects based on device-level models. Reliability estimation during operational life of an electronic system still lacks a solution especially for analog and mixed signal systems. The current work will present a novel technique for indirectly estimating reliability during operational life of an electronic system. Reliability simulations during the design stage of a potential critical performance parameter, sensitive to aging effects, over a range of input-stress voltages and working-stress temperatures have been used to generate a set of degradation values per unit time. These values are then used at the system level to estimate the degradation in that particular performance parameter and hence system reliability by regularly monitoring the input-stress voltages and working-stress temperatures. The simulation results conducted for an example target system in a LabVIEW environment show that the proposed technique is viable.

System dependability has become important for critical applications in recent years as technology is moving towards smaller dimensions. Achieving high system dependability can be supported by reliability estimations during the operational life. In addition, this requires a workflow for regularly monitoring reliability and taking necessary repair actions. This has been proposed as a possible solution where degradation in system-level performance parameters, being directly influenced by variations and degradation in device-level parameters, has been considered a potential possibility for estimating reliability during the operational life of a system. Furthermore, the degradation rate of these system-level performance parameters depends on the initial values dispersion as a result of fabrication-related process variations. This requires a database of initial and runtime system-level performance parameters at the very start and at every potentially anticipated critical time-point of the system. Therefore, initial system specifications at the design-time and runtime performance parameter measurements stored in the database are used to estimate reliability and taking necessary actions for enhancing system dependability via repair. Simulation results for an example target system in a LabVIEW environment fully support the proposed idea.

In automotive mixed-signal SoCs, the analogue/mixed-signal front-ends are of particular interest with regard to dependability. Because of the many electrical disturbances at the front-end, often (active) filters are being used. Due to the harsh environments, in some cases, degradation of these filters may be encountered during lifetime and hence false sensor information could be provided with potential fatal results. This paper investigates the influence of aging in three different types of active filters in an automotive environment, and presents an embedded instrument, which monitors this aging behaviour. The monitor can be used for flagging problems in the car console or initiate automatic correction.

A new approach towards highly reconfigurable SoCs for data-streaming multi-sensory systems is presented. As the applications are in the security arena, a very high degree of dependability should be guaranteed. For this purpose, extensive use is made of many-core processor architectures and associated embedded health-monitoring circuits. This enables the preventive (automatic) repair by spare parts or priority ranking of tasks among processors.

Most of the links in future wireless communication networks will be established over relatively short distances. This new direction in wireless communication is adopted and being developed by embedded multimedia applications leaders. Moreover, these short range communications are introduced into critical applications, where the dependability/reliability is mandatory. Thus, dependability concerns around reliability evaluation becomes an essential question to answer, and poses several challenges. Obviously, it's particularly difficult to investigate the reliability of such mixed HW/SW IPs based systems. Therefore, dependability has to be investigated at different abstractions levels, and for all components integrated into the system being designed. In this paper, we discuss the investigation of dependability in wireless short range systems. Firstly we show how a HW platform based dependability investigation can be a very interactive approach; secondly, we describe a real experience in building a wireless hardware platform for short range systems dependability analysis, and finally, based on this wireless network platform, we propose a dependability flow that takes care of the heterogeneous parts of the wireless embedded systems.

Mahalanobis distance is one of the commonly used multivariate metrics for finely segregating defective devices from non-defective ones. An associated problem with this approach is the estimation of a robust mean and a covariance matrix. In the absence of such robust estimates, especially in the presence of outliers to test-response measurements, and only a sub-sample from the population is available, the distance metric becomes unreliable. To circumvent this problem, multiple Mahalanobis distances are calculated from selected sets of test-response measurements. They are then suitably formulated to derive a metric that has a reduced variance and robust to shifts or deviations in measurements. In this paper, such a formulation is proposed to qualitatively screen product outliers and quantitatively measure the reliability of the non-defective ones. The application of method is exemplified over a test set of an industrial automobile product.

The long-term functionality of any electronic system poses some requirements on the dependability of that system. Especially for critical systems it is becoming a crucial property with increasing system complexity and shrinking technology dimensions. Analog and mixed-signal systems are an important part of these critical systems. Until now little effort has been put into dependability of analog and mixed-signal systems, especially front/back-ends. This paper presents a new system-level platform for enhancing and analyzing the dependability of analog and mixed-signal front-ends in SoCs. Markov analysis has been used to theoretically investigate the dependability enhancement of these analog and mixed-signal front-ends based on this platform. Simulations in VHDL-AMS have also been conducted for an example target system consisting of a temperature sensor, operational amplifier and ADC to illustrate this platform. The gain parameter of the whole system, taken as an example of potential dependability hazard, has been investigated and enhanced based on this platform. The results show that this proposed platform is effective and has the potential to investigate and enhance dependability at system level.

This paper presents a technique for reducing CPU time to perform simulation-based fault-injection experiments in complex SoCs. This technique is fully compatible with commercial HDL simulators with no requirement to develop dedicated compilers. This approach can be easily applied to complex SoC models, as it is not required to modify the top-level modules of design, moreover, it can inject a wide range of fault models in the design and finally it can achieve a competitive reduction in terms of CPU time compared with other time-accelerated simulation-based approaches. These goals are achieved by using simulator-commands along with partial code modification techniques. The experimental results show that the proposed technique is able to reduce the CPU time by a factor ranging from 27% to 67% compared with typical simulation-based fault-injection approaches and by a factor of 10% compared with time-accelerating simulation-based techniques.

Mahalanobis distance is one of the commonly used multivariate metrics for finely segregating defective devices from non-defective ones. An associated problem with this approach is the estimation of a robust mean and a covariance matrix. In the absence of such robust estimates, especially in the presence of outliers to test-response measurements, and only a sub-sample from the population is available, the distance metric becomes unreliable. To circumvent this problem, multiple Mahalanobis distances are calculated from selected sets of test-response measurements. They are then suitably formulated to derive a metric that has a reduced variance and robust to shifts or deviations in measurements. In this paper, such a formulation is proposed to qualitatively screen product outliers and quantitatively measure the reliability of the non-defective ones. The application of method is exemplified over a test set of an industrial automobile product.

Nowadays highly dependable electronic devices are demanded by many safety-critical applications. Dependability attributes such as reliability and availability/maintainability of a many-processor system-on-chip (MPSoC) should already be examined at the design phase. Design for dependability approaches such as using available fault-free processor-cores and introducing a dependability manager infrastructural IP for self-test and evaluation can greatly enhance the dependability of an MPSoC. This is further supported by subsequent software-based repair. Design choices such as test fault coverage, test and repair time are examined to optimize the dependability attributes. Utilizing existing infrastructures like a network-on-chip (NoC) and tile-wrappers are needed to ensure a test can be performed at application run-time. An example design following the proposed design for dependability approach is shown. The MPSoC has been processed and measurement results have validated the proposed dependability approach.

In the conventional ADC production test method, a high-quality analogue sine wave is applied to the Analogue-to-Digital Converter (ADC), which is expensive to generate. Nowadays, an increasing number of ADCs are integrated into a system-on-chip (SoC) platform design, which usually contains a digital embedded processor. In such a platform, a digital pulse wave is obviously less expensive to generate than an accurate analogue sine wave. As a result, the usage of a digital pulse wave has been investigated to test ADCs as the test stimulus. In this paper, the ability of a digital adaptive pulse wave for ADC testing is presented via the measurement results. Instead of the conventional FFT analysis, a time-domain analysis is exploited for post-processing, from which a signature result can be obtained. This signature can distinguish between faulty devices and the fault-free devices. It is also used in the machine-learning-based test method to predict the dynamic specifications of the ADC. The experimental results of a 12-bit 80 M/s pipelined ADC are shown to evaluate the sensitivity and accuracy of using a pulse wave to test an ADC.

Daily experience with product designers, test and diagnosis engineers it is realized that the depth of interaction among them, ought be high for sucessfull diagnosis of analogue circuits. With this knowledge in mind, a responsibility was undertaken to choose a popular diagnostic method and define a systematic procedure that binds together the knowledge of a product from a design, test and diagnostic engineer. A set of software utilities was developed that assists in automating these procedures and in collecting appropriate data for effective diagnosis of analogue circuits. This paper will discuss the chosen methodology for diagnosis and the associated procedures for block-level diagnosis of analogue electronic circuits in detail. The paper is concluded with an illustration of the methodology and the related procedures of an industrial automotive voltage regulator circuit as a representative example.

Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since the scan-based test is performed on-chip via the NoC at application run-time, it needs to share the NoC bandwidth with other applications. Instead of reserving sufficient NoC bandwidth for the test, the authors propose a novel way to carry out scan-based tests by dynamically pausing and resuming the test data flow to accommodate the fluctuating communication bandwidth available on the NoC. The test stimuli application and test response collection processes are decoupled to meet the global timing constraint. The many-core processor, IIP and the NoC have been implemented in synthesizable VHDL. Simulation results show the correct application of standard structural test patterns to the processing tiles and the test response collection at run-time using the proposed approach.

A systematic approach to construct an effective multivariate test response model for capturing manufacturing defects in electronic products is described. The effectiveness of the model is demonstrated by its capability in reducing the number of test-points, while achieving the maximal coverage attainable by the specific test method on an industrial circuit.

A new method is presented to test dynamic parameters of Analogue-to-Digital Converters (ADC). A noisy and nonlinear pulse is applied as the test stimulus, which is suitable for a multi-site test environment. The dynamic parameters are predicted using a machine-learning-based approach. A training step is required in order to build the mapping function using alternate signatures and the conventional test parameters, all measured on a set of converters. As a result, for industrial testing, only a simple signature-based test is performed on the Devices-Under-Test (DUTs). The signature measurements are provided to the mapping function that is used to predict the conventional dynamic parameters. The method is validated by simulation on a 12-bit 80 Ms/s pipelined ADC with a pulse wave input signal of 3 LSB noise and 7-bit nonlinear rising and falling edges. The final results show that the estimated mean error is less than 4% of the full range of the dynamic specifications.

Recent advances in the semiconductor industry enable the integration of many processing units on a single die and new processors are often included into large many-core SoCs. The dependability of such a many-core processor is essential for many mission-critical applications. Ideas such as the Know-Good-Tile concept [1] or majority-voting among tiles [2] have been proposed to explore the possibility to enhance the dependability of a many-core processor.

As CMOS process technology advances towards 32 nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip is designed using 64 reconfigurable Xentium tile processors. A functional dependability analysis for this application was carried out following the IEC standard 62347. To meet the dependability requirements, a dedicated infrastructural IP (IIP) and supporting software and hardware have been designed and included as part of the dependability infrastructure of the chip. This IIP can periodically verify the correctness of the tile processors and coordinate the run-time mapping reconfiguration software to isolate the faulty tiles at run time and assign spare processors for the open DSP tasks. Dependability graphs show a significant improvement of the application chip incorporating the design-for-dependability hardware and software.

This paper reports two novel algorithms based on time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both algorithms, a pulse signal, in its slightly adapted form to allow sufficient time for converter settling, is taken as the test stimulus reliving the burden placed on accuracy requirement of excitation source. The objective of the test scheme is not to completely replace traditional specification-based tests, but to provide a reliable method for early identification of excessive parameter variations in production test that allows quickly discarding of most of the faulty circuits before going through the conventional test. The efficiency of the methods is validated on a 6-bit flash ADC.

The introduction of MEMS in microsystems is progressing rapidly. The high-volume testing of these multi-domain systems are often relatively cumbersome in comparison with pure electrical tests, because of non-electrical stimuli and/or response. It requires currently custom-made test set-up. Also the quality of tests is difficult to quantify. Hence, structural tests seem more appropriate, but this requires a lot of research and new approaches.

Many of the semiconductor technologies are already facing limitations while new-generation data and telecommunication systems are implemented. Although in its infancy, superconductor electronics (SCE) is capable of handling some of these high-end tasks. We have started a defect-oriented test methodology for SCE, so that reliable systems can be implemented in this technology. In this paper, the details of the study on the Rapid Single-Flux Quantum (RSFQ) process are presented. We present common defects in the SCE processes and corresponding test methodologies to detect them. The (measurement) results prove that we are able to detect possible random defects for statistical purposes in yield analysis. This paper also presents possible test methodologies for RSFQ circuits based on defect oriented testing (DOT).

The testable design and testing of a fully software-controllable lab-on-a-chip, including a fluidic array of FlowFETs, control and interface electronics is presented. Test hardware is included for detecting faults in the DMOS electro-fluidic interface and the digital parts. Multidomain fault modeling and simulation shows the effects of faults in the (combined) fluidic and electrical parts. The fault simulations also reveal important parameters of multi-domain test-stimuli, e.g. fluid velocity, for detecting both electrical and fluidic defects.

During the last few years, new synchronization techniques to send data between ICs at increasingly high data-rates have been developed. Some of them rely on digital delay lines. The timing accuracy of the delay lines is crucial for good functionality of the synchronization mechanism. This paper presents a strategy to measure the tap-delays of a digital delay-line, using the well-known oscillation technique. The occurring measurement error for the presented technique has been calculated. Towards the end of the paper, a new delay-line scheme is shown. The tap-delay, measurement becomes much more accurate for this delay-line than for a standard delay-line.

A test method for asynchronous handshake circuits is presented that is based on synchronous full-scan techniques. The method adds a synchronous test mode to the circuit, in which the entire circuit is controlled by external clocks. This enables the use of conventional test generation tools. The method resulted in an operational flow, capable of automatically testing any handshake circuit with test-quality equal to synchronous circuits. Several circuits have been evaluated, demonstrating over 99% stuck-at fault coverage.

This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multifrequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DFT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.

Recent developments in the field of MEMS indicate a clear move toward systems, rather than just individual components. Design and fabrication of these components include new methods and techniques. Does testing require new methodologies and tools ? Will we be able to include MEMS in the SoCs flow ?

This paper presents a general economic modeling methodology for digital semiconductor production test approaches. The methodology can be used to quantify trade-offs and evaluate test approaches, including distributed test across test insertions, multi-site test, on-chip/off-chip test trade-offs and ATE architectural tradeoffs, with modeled cost contributions that include test time, die area, yield, time-to-market, and engineering effort. It allows one to forecast how those test approaches scale with technology progress. The economic models are modular and expandable. The modeling methodology will be illustrated on various test approaches.

This paper describes a new approach in the high level design and test of transport-triggered architectures (TTA), a special type of application specific instruction processors (ASIP). The proposed method introduces the test as an additional constraint, besides throughput and circuit area. The method, that calculates the testability of the system, helps the designer to assess the obtained architectures with respect to test, area and throughput in the early phase of the design and selects the most suitable one. In order to create the templated TTA, the "MOVE" framework has been addressed. The approach is validated with respect to the "Crypt" Unix application.

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addressed.

Microsystems have many characteristic features of small printed-circuit boards as well as large ICs. Hence, many testing techniques developed for these implementation forms can he used for microsystems. It is the question whether these test techniques cover all elements involved in the large variely of microsystems, such as kartly) non-electrical components.

This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC. The interface with the system designer is user-friendly and together with an efficient search mechanism this expert system can be used as a framework for all types of macros. This tool will be used in a self-test compiler, which generates the layout of self-testable macros automatically. The self-test compiler can be part of a silicon compilation system and thus contribute to the integration of testability into the design process.>

A method is presented to analyze the testability of both linear and nonlinear analog systems. It combines a rank-test algorithm with statistical methods. The algorithm will find sets of dependent parameters and determine whether it is possible to calculate a certain parameter with sufficient accuracy. it also determines a subset of appropriate measurements if redundant measurements are present.>

A method is presented to analyze the testability of both linear and nonlinear analog systems. It combines a rank-test algorithm with statistical methods. The algorithm finds sets of inseparable parameters and determines whether it is possible to calculate a certain parameter with efficient accuracy. It also determines a subset of appropriate measurements if redundant measurements are present.>

A new method to implement multiple-valued logic in large scale integrated circuits is introduced. The data are represented by discrete amounts of charge in a charge-coupled device. In this paper the design principles and realizations in four-valued logic of a minimum and maximum circuit, a complement circuit, a literal a successor, and an adder are presented. Also, the designs of a binary-to-quaternary converter and vice versa are discussed. Charge-coupled devices offer low-power consumption, high-packing density, and the possibility to perform MOST-IC compatible multiple-valued logic in any arbitrary radix.